Electrical Fuse Rupture Circuit for Semiconductor Memory Repair
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Solution Overview
Problem
Conventional electrical fuse rupture methods in semiconductor memory apparatuses are inefficient, particularly in packaged states, as they require repeated external commands and prolonged testing times to ensure proper fuse rupture operations, leading to increased manufacturing costs and reduced yield due to the need for redundant memory cells.
Innovation Solution
An electrical fuse rupture circuit with a fuse rupture control block and a rupture verification determination block that receives failure address signals, performs fuse rupture operations in response to test and reset signals, and outputs rupture address signals to verify the success of the operation, thereby reducing the need for repeated external commands and shortening testing times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the electrical fuse rupture operation is performed by repeatedly applying external commands and evaluating results, then the reliability of fuse rupture is improved, but the testing time is extended
Solution Approach 1:
The patent implements an internal feedback mechanism where the fuse rupture circuit automatically evaluates the result of each fuse rupture operation and generates a reset signal based on whether the operation was successful. This internal feedback loop eliminates the need for repeated external commands and evaluations, thereby maintaining reliability while reducing testing time.
Solution Approach 2:
The fuse rupture circuit is designed to perform self-verification of the fuse rupture operation. The circuit automatically determines whether the fuse rupture was successful and generates appropriate reset signals without requiring external continuous monitoring or repeated commands, enabling the system to serve itself in the verification process.
2Reliability
If redundant memory cells are added to cope with failures, then the reliability of the semiconductor memory apparatus is improved, but the manufacturing complexity and cost increase
Solution Approach 1:
The patent performs the fuse rupture operation and verification before the actual memory cell replacement is needed. By pre-establishing the ability to detect and mark failed memory cells through fuse rupture, the system prepares redundant memory cells for potential replacement without immediately increasing operational complexity. The verification mechanism ensures that only properly replaced cells are activated.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The electrical fuse rupture circuit ensures proper fuse rupture operations with reduced testing time and increased efficiency, allowing for faster identification and replacement of faulty memory cells, thereby improving manufacturing yield and reducing waste.
Implementation Method 1
The electrical cutting method is a method in which cutting accomplished by applying overcurrent to target fuses
Implementation Method 2
the laser cutting method is a method in which target fuses requiring cutting are blown using a laser beam
Data Source
AI summary
A semiconductor memory device including circuitry for detecting and repairing memory cell failures in a test mode. The memory cell repair process is conducted in a manner that effectively eliminates unnecessary fuse rupture operations and verify operations in a test mode, thus reducing product test time.