Memory Controller Bit Line Voltage Control for Write Disturb Prevention
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Solution Overview
Problem
Existing memory devices face issues with write disturbs and leakage paths during write operations, which affect endurance performance and read margin, especially when unselected bit lines are left floating.
Innovation Solution
Supplying unselected bit line, word line, and source line voltages to unselected memory cells to prevent or minimize write disturbs and leakage paths, thereby maintaining the logic state of write-inhibited memory cells and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If unselected bit lines are left floating during write operations, then device complexity is reduced, but write disturbs and leakage paths increase affecting endurance performance and read margin
Solution Approach 1:
The patent applies preliminary action by pre-setting unselected bit lines to a specific voltage level (e.g., ground or reference voltage) before write operations begin. This preliminary voltage assignment prevents write disturbs and leakage paths from occurring during the write operation, thereby improving endurance performance and read margin without requiring complex real-time control circuits.
Solution Approach 2:
The patent employs equipotentiality by maintaining unselected bit lines at a defined voltage potential (equipotential state) during write operations. By keeping these lines at a stable voltage level rather than leaving them floating, the patent prevents potential differences that would cause leakage currents and write disturbs, thus improving reliability while using simple voltage assignment logic.
2Reliability
If unselected bit lines are supplied with voltage to prevent write disturbs, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by selectively applying voltage only to unselected bit lines that require protection from write disturbs, rather than applying voltage universally to all bit lines. This selective approach ensures reliability improvement in critical areas while minimizing unnecessary power consumption in non-critical areas, achieving an optimal balance between endurance performance and power efficiency.
Solution Approach 2:
The patent uses parameter changes by dynamically adjusting the voltage level of unselected bit lines based on operational requirements. During write operations, unselected bit lines are assigned specific voltage levels to prevent write disturbs, while during read or idle operations, these lines may be placed in low-power states. This dynamic parameter adjustment improves endurance when needed while reducing power consumption during other operations.
Data Source
AI summary
A memory controller has a bit line driver configured to supply a selected bit line voltage to a selected bit line and an unselected bit line voltage to an unselected bit line. The selected bit line is coupled to a selected memory cell, and the unselected bit line is coupled to an unselected memory cell. The memory controller further has a word line driver configured to supply a selected word line voltage to a selected word line and an unselected word line voltage to an unselected word line. The selected word line is coupled to the selected memory cell, and the unselected word line is coupled to the unselected memory cell. The unselected bit line voltage is equal to or higher than a difference between the unselected word line voltage and a threshold voltage of the unselected memory cell.