Fuse Circuit Sequential Latch Reset for Peak Current Reduction
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Solution Overview
Problem
Existing semiconductor fuse circuits face challenges in efficiently resetting latch blocks to store and provide fuse data without peak current consumption and stable operation, particularly in semiconductor memory apparatuses.
Innovation Solution
The proposed fuse circuit includes an E-fuse array, a latch block with multiple latch groups, and a control block that generates and enables latch reset signals in response to an apparatus reset signal and clock signal, allowing sequential resetting of latch groups and decentralized power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the latch block is reset simultaneously, then the reset operation is simple and fast, but peak current consumption occurs and stable operation is compromised
Solution Approach 1:
The latch block is divided into multiple latch groups (first latch group and second latch group), which are reset sequentially rather than simultaneously. The control block generates separate reset signals for each group, enabling staged reset operations that distribute current consumption over time and avoid peak current while maintaining reliable reset functionality.
2Reliability
If the latch block is reset sequentially, then power consumption is decentralized and stable operation is achieved, but the control complexity increases
Solution Approach 1:
The latch block is segmented into multiple latch groups that can be controlled independently. Each latch group has its own reset signal input, allowing the control block to manage them separately. This segmentation enables decentralized power consumption while maintaining manageable control complexity through modular signal generation.
Solution Approach 2:
The control block is designed to generate the necessary reset signals in advance based on clock signals and reset inputs. By preparing the control logic beforehand, the system achieves sequential reset without adding significant control complexity during operation, as the signal generation follows a predetermined pattern.
3Reliability
If multiple latch groups are used, then power consumption is distributed and stable operation is achieved, but the device area increases
Solution Approach 1:
The latch block is divided into multiple latch groups that share common control logic and signal paths where possible. By segmenting the latch functionality while reusing control circuitry and signal distribution networks, the area increase is minimized compared to implementing separate reset circuits for each latch, achieving stable operation with controlled area overhead.
Data Source
AI summary
A fuse circuit includes an E-fuse array including a plurality of E-fuse elements configured to store fuse data; a latch block including a plurality of latch groups configured to latch the fuse data read from the E-fuse array; and a control block configured to output latch reset signals corresponding to the plurality of latch groups in response to an apparatus reset signal and a clock signal, wherein the control block sequentially enables the latch reset signals.