Memory Controller Segmentation for Mixed Volatile Non-Volatile DDR Access
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Solution Overview
Problem
The integration of non-volatile and volatile memory devices on the same memory bus is challenging due to their disparate access times, which do not align with the deterministic timing specifications of the DDR memory interface, limiting the ability to mix memories with different latency properties and hindering performance enhancements.
Innovation Solution
A device comprising a read unit, a store unit, and a return unit that fetches data in response to a first read request and returns it in response to a subsequent read request, allowing non-volatile memory devices with longer latency to share a DDR interface with standard DIMMs, enabling direct access to higher capacities without additional memory interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If non-volatile memory devices are integrated on the same memory bus with volatile memory devices, then memory capacity and non-volatility are improved, but access time performance deteriorates due to slower non-volatile memory access speeds
Solution Approach 1:
The memory system is segmented into volatile memory devices for fast access and non-volatile memory devices for high capacity storage. The memory controller divides memory access operations between these two types of devices based on their respective strengths, allowing the system to achieve both high capacity and fast access performance simultaneously.
Solution Approach 2:
A memory controller acts as an intermediary between the host system and the mixed memory devices. It manages the disparate timing properties of volatile and non-volatile memory devices, translating host memory access requests into appropriate commands for each device type and buffering data to mask the slower access times of non-volatile memory.
2Device complexity
If non-volatile and volatile memory devices share the same DDR memory interface, then device complexity is reduced, but timing specification compliance becomes difficult due to deterministic timing requirements
Solution Approach 1:
The memory controller serves as an intermediary that absorbs the timing differences between volatile and non-volatile memory devices. It implements timing recovery mechanisms and uses buffers to ensure that data is delivered to the host system within the deterministic timing requirements of the DDR interface, regardless of the slower access times of non-volatile memory.
Solution Approach 2:
The system performs preliminary actions by pre-fetching data from non-volatile memory into buffers before it is needed by the host system. This allows the memory controller to mask the slower access times and deliver data within the required timing specifications, ensuring compliance with deterministic timing requirements.
3Ease of operation
If standard DDR memory interface is used for both volatile and non-volatile memory, then ease of operation is improved, but performance enhancement is limited by the slower access times of non-volatile memory
Solution Approach 1:
The memory system segments operations between volatile and non-volatile memory based on performance requirements. Frequently accessed data is stored in volatile memory for fast access, while less frequently accessed data resides in non-volatile memory. The memory controller intelligently manages this segmentation to maintain high overall system performance.
Solution Approach 2:
The system dynamically changes operational parameters such as cache line sizes, prefetch distances, and buffer depths based on workload characteristics. This allows the memory controller to optimize performance for different access patterns while maintaining compatibility with the standard DDR interface.
Data Source
AI summary
First and second read requests are received. First data is fetched in response to the first read request. The fetched first data is then stored. The fetched first data corresponds to an address of the first read request. The fetched first data is returned in response to the second read request.