Flash Memory Cell Array Segmentation for Leakage Current Control
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Solution Overview
Problem
As the capacity and integration of semiconductor memory devices increase, the leakage current between memory blocks connected to the same bit line increases, reducing the sensing margin between programmed and erased cells, leading to errors in the device.
Innovation Solution
Dividing memory blocks into units and connecting common source lines to a source voltage generator through switching units, allowing for controlled application of source voltage and positive bias, thereby reducing leakage current during read operations and maintaining the current ratio between program and erase cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory blocks connected to the same bit line is increased to increase device capacity, then the storage capacity is improved, but the leakage current increases and sensing margin decreases
Solution Approach 1:
The memory blocks connected to the same bit line are divided into multiple groups, with each group having an independent common source line. This segmentation isolates the leakage current paths, so that when one group is being read, only its dedicated common source line is at 0V while other common source lines are at positive voltage, preventing leakage current from affecting the sensing operation.
2Device complexity
If more memory blocks share the same common source line to reduce complexity, then device complexity is reduced, but leakage current increases and affects read operation accuracy
Solution Approach 1:
Instead of having all memory blocks share a single common source line, the patent divides them into multiple groups, each with its own common source line. This increases the number of common source lines but reduces the number of blocks per line, thereby isolating leakage current paths and improving read accuracy.
Solution Approach 2:
The patent introduces switching units as intermediary components between the voltage generator and each common source line. These switching units control which common source lines are connected to the 0V potential during read operations, enabling selective isolation of unselected blocks and preventing their leakage current from affecting the sensing operation.
3Ease of operation
If 0V is applied to common source line during read operation to enable sensing, then read operation is enabled, but leakage current from unselected blocks increases
Solution Approach 1:
The patent segments the common source lines so that during a read operation on a specific group, only the common source line for that group is set to 0V, while common source lines for other groups are maintained at positive voltage. This segmentation prevents leakage current from unselected blocks while still enabling proper sensing for the selected group.
Solution Approach 2:
The patent applies different voltage conditions to different common source lines based on their associated memory blocks. During a read operation, the common source line for the selected group has 0V applied locally, while other common source lines have positive voltage applied, creating local quality differences that enable reading while suppressing leakage current.
Data Source
AI summary
A cell array of a flash memory device includes first and second memory block units, and a voltage generator. Each of the first and second memory block units includes a plurality of memory blocks having a plurality of memory cells. The voltage generator outputs a source voltage, a power supply voltage and a positive bias to the first and second memory block units. The first and second memory block units are connected in parallel through a bit line.