Multilevel Memory Cell Grouping for Silicon Area Reduction
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Solution Overview
Problem
Multi-level memory devices face inefficiencies in silicon area occupation due to the use of additional cells for storing a single bit, leading to reduced information density and increased cell count, especially when cells can only assume three levels.
Innovation Solution
The method involves grouping bits into sets (triplets or quintuplets) and storing them in pairs of three-level or six-level cells, respectively, with the remaining bits of a word stored together in dedicated cells, reducing the number of cells required per page and optimizing silicon area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional methods store each bit in separate cells or use one cell per bit, then reliability is maintained, but silicon area occupation increases and information density decreases
Solution Approach 1:
The patent merges multiple bits into groups (triplets or quintuplets) and stores them in pairs of multilevel cells. Specifically, three bits are encoded into two ternary values and stored in a pair of three-level cells, or five bits are encoded into two quaternary values and stored in a pair of six-level cells. This combining approach achieves higher information density while reducing the number of cells required per page.
Solution Approach 2:
The patent changes the parameter of cell logic states from traditional two-level (binary) to multilevel (three-level or six-level) cells. By increasing the number of logic states per cell, the system can store more information in fewer cells, thereby improving information density and reducing silicon area occupation.
2Area of stationary object
If multilevel cells are used to reduce cell count, then silicon area is saved, but complexity of bit manipulation increases
Solution Approach 1:
The patent segments bits into fixed-size groups (triplets of three bits or quintuplets of five bits) that can be systematically encoded and decoded. This segmentation approach, combined with dedicated coding circuits, manages the complexity of bit manipulation by breaking down the process into manageable, repetitive operations rather than handling arbitrary bit patterns.
Solution Approach 2:
The patent introduces coding circuits as intermediary components that handle the complex conversion between binary bit strings and ternary/quaternary values. These coding circuits act as mediators between the input data and the multilevel memory cells, managing the complexity of bit manipulation while allowing the memory cells themselves to operate with simpler, standardized encoding schemes.
3Area of stationary object
If three-level cells are used instead of two-bit per cell devices, then area occupation is reduced, but error correction requirements increase
Solution Approach 1:
The patent combines multiple bits into groups that are stored in pairs of three-level cells, creating a redundant structure that facilitates error detection and correction. By encoding three bits into two ternary values or five bits into two quaternary values, the system creates inherent redundancy that can be used for error correction while maintaining area efficiency.
Data Source
AI summary
A memory has an array of k-level cells, organized into pages of words, each storing a string of bits. The memory device includes a coding circuit input with strings of N bits, and generates corresponding k-level strings. A program circuit is input with the k-level strings to stores in groups of c cells with k levels. A read circuit reads data stored in groups of c cells with k levels and generates k-level strings. A read decoding circuit is input with k-level strings read from groups of c cells with k levels to generate strings of N bits. The words of each page are grouped in groups of words, each word including groups of c cells with k levels, and at least one remaining bit of the word being stored, with corresponding remaining bits of other words of the page, in a group of c cells with k levels.