Sequential Memory Access Method Eliminates Discharge Periods
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory technologies face inefficiencies in operation time and power consumption due to the need for discharge periods to clear residual charges, leading to increased leakage current and unpredictable errors, especially as the number of memory cells per bit line increases.
Innovation Solution
A sequential memory method that eliminates the discharge period by equalizing voltage levels of transistors to ground voltage, transforming terminal voltages to source and drain voltages in a controlled manner, allowing for high-speed operation without the need for discharge steps, thereby reducing power consumption and operation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a discharge period is performed to clear residual charges in conventional memory, then leakage current and errors are reduced, but operation time increases and power consumption rises
Solution Approach 1:
The patent extracts and eliminates the discharge period from the memory operation cycle. By using a sequential access architecture where bit lines are sequentially connected to different memory cells, residual charges are naturally cleared during the sequential switching process, making the separate discharge step unnecessary. This removes the time-consuming discharge operation while maintaining reliability.
Solution Approach 2:
The patent implements continuous useful action by eliminating idle discharge periods. The memory system continuously performs productive operations (charging, sensing, switching) without interruption by discharge steps. The sequential bit line connection ensures that each bit line is fully utilized for its intended memory cell access before being switched to the next cell, maximizing operational efficiency.
2Quantity of substance
If the number of memory cells per bit line increases, then memory density improves, but discharge period increases and power consumption rises
Solution Approach 1:
The patent segments the bit lines into separate sequential channels, with each bit line dedicated to accessing a specific memory cell. This segmentation prevents the cumulative capacitance effect that occurs when multiple memory cells share a common bit line. Each bit line handles only one memory cell at a time, so power consumption does not increase with memory density.
Solution Approach 2:
The patent transitions from a two-dimensional array structure where multiple cells share bit lines to a sequential one-dimensional access pattern. By adding the time dimension to the access mechanism, the system achieves high density without the power penalty, as each bit line is reused sequentially rather than being shared simultaneously by multiple cells.
3Quantity of substance
If the number of memory cells per bit line increases, then memory density improves, but reading/programming time increases
Solution Approach 1:
The patent segments the memory access process into sequential time slots, with each bit line dedicated to a specific memory cell during its time slot. This segmentation eliminates the bottleneck caused by charging/discharging large capacitive loads associated with multiple shared bit lines. Each access operation completes quickly because it involves only one memory cell and one bit line, maintaining high speed despite high density.
Solution Approach 2:
The patent introduces dynamic reconfiguration of bit line connections through sequential switching. The bit lines are dynamically connected to different memory cells in different time periods, allowing the system to maintain fast access times by ensuring each bit line operates with a manageable capacitive load at any given moment, while achieving high overall density through the sequential arrangement.
Data Source
AI summary
A method for accessing a memory sequentially. The memory has (m+1) bit lines and at least one row of transistors, wherein m is a positive integer. This method includes the following steps. First, voltage levels of first and second terminals of the transistors are equalized to a ground voltage in a pre-discharge period. Next, the voltage levels of the first and second terminals of the nth transistor are respectively transformed into a source voltage and a drain voltage in an nth reading period, and the voltage level of the second terminal of the (n+1)th transistor is transformed into an isolation voltage, wherein n is a positive integer smaller than m. Thereafter, the voltage levels of the first and second terminals of the mth transistor are respectively transformed into the source voltage and the drain voltage in an mth reading period. The source voltage equals the ground voltage.