Memory Peripheral Circuit Parallel Initialization
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Solution Overview
Problem
Current memory manufacturing technologies face challenges in reducing the time occupied by initialization operations, which affect program performance by delaying the program operation.
Innovation Solution
The proposed solution involves a memory system where the peripheral circuit receives a program command, address, data, and confirmation command, and performs program operations after completing at least two initialization operations. These initialization operations overlap in time with the receipt of program-related commands and data, allowing for parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If initialization operations are performed sequentially before program operation, then memory reliability is ensured, but program time is increased
Solution Approach 1:
The patent applies preliminary action by performing initialization operations in advance before the program operation is fully executed. The peripheral circuit performs at least two initialization operations (such as checking reference voltage, detecting bad blocks, and verifying memory cell status) before initiating the program operation, ensuring that the memory is ready for reliable programming while reducing the overall time required.
Solution Approach 2:
The patent merges the initialization operations with the program operation process. The peripheral circuit integrates multiple initialization tasks (reference voltage check, bad block detection, memory cell status verification) into a combined process that overlaps with the program operation timing, allowing these operations to be performed concurrently rather than sequentially.
2Reliability
If multiple initialization operations are performed, then program operation reliability is improved, but processing complexity is increased
Solution Approach 1:
The patent segments the initialization process into distinct operational steps: first initialization operation (checking reference voltage, detecting bad blocks) and second initialization operation (verifying memory cell status). Each segment is performed by the peripheral circuit in a structured manner, making the complex initialization process manageable and systematic while ensuring comprehensive reliability checking.
Data Source
AI summary
Examples of the present disclosure provide a memory and operating method thereof, a memory system and a readable storage medium. The memory includes an array of memory cells and a peripheral circuit coupled to the array of memory cells; the peripheral circuit is configured to: receive a program command, a program address, program data, and a program confirmation command which correspond to a program operation, and perform the program operation on the array of memory cells after performing at least two initialization operations. The process of receiving the program command, the program address, the program data, and the program confirmation command which correspond to the program operation and the process of performing the at least two initialization operations at least partially overlap in time.