Flash Memory Sense Architecture Flexible Sector Routing
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Solution Overview
Problem
Conventional flash memory architectures are constrained by the requirement for an even number of sectors and uniform sector sizes, leading to inefficient use of chip area and increased parasitic impedances, which degrade sensing performance and noise margin.
Innovation Solution
A sense architecture that allows for flexible sector sizes and numbers by routing sense and reference lines from adjacent column decode circuits to the same differential amplifier, reducing chip area and parasitic impedances, and eliminating the need for physical cross-overs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flash memory architecture uses uniform sector sizes and requires even number of sectors, then balanced sense amplifier operation is maintained, but chip area efficiency deteriorates and parasitic impedances increase
Solution Approach 1:
The memory array is divided into sectors with flexible sizes that can be independently configured. Each sector contains memory cells organized in rows and columns, allowing non-uniform sector dimensions while maintaining proper sense amplifier operation through localized column decode circuits and bit line routing.
Solution Approach 2:
Different sectors can have different sizes and characteristics optimized for specific functions. The column decode circuits are positioned to serve local groups of columns, allowing each sector to be tailored with appropriate dimensions while maintaining consistent sensing performance through localized reference bit lines.
2Ease of manufacture
If conventional architecture uses uniform sector sizes, then sense amplifier balancing is simplified, but adaptability to different memory configurations deteriorates
Solution Approach 1:
The memory architecture allows dynamic configuration of sector sizes and numbers based on application requirements. The column decode circuits and bit line routing are designed to adapt to varying sector dimensions, enabling flexible memory layouts while maintaining proper sense amplifier operation through programmable or configurable addressing logic.
Solution Approach 2:
The column decode circuits and sense amplifier architecture are designed to handle multiple sector configurations universally. The same basic circuit structure can serve different sector sizes and numbers by adjusting control signals, eliminating the need for separate dedicated circuits for each configuration.
3Ease of operation
If conventional architecture routes sense lines across the chip, then all column decode circuits can access sense amplifier, but parasitic impedances increase and sensing speed deteriorates
Solution Approach 1:
The chip is divided into localized regions with column decode circuits positioned close to the memory cells they serve. Sense lines are routed locally within each sector rather than across the entire chip, reducing the length of conductors and minimizing parasitic inductance and resistance while maintaining access to all column decode circuits.
Solution Approach 2:
Reference bit lines are introduced as intermediary elements that provide stable reference voltages to sense amplifiers. These reference bit lines are positioned adjacent to the sense lines, allowing for balanced impedance matching and reduced parasitic effects through localized reference provision rather than distant reference sources.
4Adaptability or versatility
If conventional architecture requires physical cross-overs for routing, then interconnection flexibility is maintained, but manufacturing complexity increases
Solution Approach 1:
Instead of routing sense lines across the chip and using physical cross-overs to connect different regions, the architecture inverts the approach by placing column decode circuits and bit lines in close proximity to the memory cells. This eliminates the need for long cross-chip routes and physical cross-overs, simplifying the routing structure while maintaining interconnection flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces chip area requirements, improves sensing speed, and enhances noise margin by balancing parasitic impedances and simplifying interconnection routing, enabling more efficient and flexible flash memory implementation.
Implementation Method 1
the sense amplifier circuitry includes a differential amplifier that compares a level at one input that is defined by the state of the selected memory cell with a reference level established by a reference circuitry present at its other input
Implementation Method 2
programming (i.e., written) by biasing it so that hot carrier injection causes electrons to become trapped on an electrically isolated transistor gate element
Implementation Method 3
erased by biasing the transistor so that the floating-gate electrons tunnel to the source or drain
Data Source
AI summary
Memory architecture, such as for a flash EEPROM memory embedded within a processor or other large scale integrated circuit, and including differential sense circuitry. The memory includes an array of memory cells in rows and columns, and organized into sectors, each sector split into portions. Columns of the array are grouped into small groups from which a final stage column decode selects a column from the group based on the least significant bits of the column address. Adjacent groups of columns are paired, with a selected column from each group coupled to a differential input of the sense amplifier, but with one of the selected columns associated with an unselected sector portion and thus serving as a dummy bit line. Conductor routing is simplified, and chip area is reduced, by maintaining unselected column groups adjacent or nearby to selected column groups.