Flash Memory Metablock Size Reduction via Plane Interleaving
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Solution Overview
Problem
The challenge in flash memory devices is to maximize parallel plane write performance while minimizing system metablock size, as small metablock sizes reduce the number of planes that can be operated in parallel, increasing programming time and conflicting with standards.
Innovation Solution
The method involves iteratively writing data in parallel across multiple planes using plane interleaving and page swapping, allowing for sequential ordering of data within the planes, which enables efficient storage and reduces write amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If metablock size is kept small to comply with standards, then standard compliance is achieved, but the number of planes that can be operated in parallel is reduced, increasing programming time
Solution Approach 1:
The patent segments the metablock into multiple sub-metablocks, each associated with different planes. This allows the system to comply with standard metablock size requirements while internally dividing the data into smaller units that can be distributed across multiple planes for parallel processing, thereby maintaining both standard compliance and high programming throughput.
Solution Approach 2:
The patent introduces a new dimension of organization by creating multiple sub-metablocks within a single metablock structure. This dimensional transformation allows the system to maintain the external appearance of standard-compliant metablock sizes while internally organizing data to enable parallel plane operations, effectively resolving the contradiction between size constraints and parallelism requirements.
2Productivity
If metablock size is increased to enable more parallel plane operations, then programming time is reduced, but standard compliance is violated
Solution Approach 1:
By segmenting the metablock into multiple sub-metablocks that can be processed in parallel across different planes, the system achieves the productivity benefits of larger metablocks without actually increasing the external metablock size, thus maintaining standard compliance while improving programming speed.
Solution Approach 2:
The patent performs preliminary organization of data into sub-metablocks before the actual programming operation. This pre-processing step enables the system to prepare data in a format that maximizes parallel plane utilization while ensuring that the final programmed structure adheres to standard metablock size requirements.
3Device complexity
If sequential writing is used to maintain simple metablock structure, then device complexity is reduced, but parallel plane write performance is not maximized
Solution Approach 1:
The patent segments the writing process into multiple independent sub-metablock operations that can be executed in parallel across different planes. Each sub-metablock maintains a simple structure, but the collective operation achieves high parallel write performance without significantly increasing overall device complexity.
Solution Approach 2:
The patent transforms the sequential writing approach into a multi-dimensional parallel writing structure by organizing data into sub-metablocks that can be written simultaneously to different planes. This dimensional change enables parallel performance improvement while keeping individual sub-metablock structures simple and manageable.
Data Source
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AI summary
Methods and systems are disclosed herein for storing data in a memory device. Data for multiple pages is written in parallel using plane interleaving. For example, in a four plane write, a first set of four pages are written in the following sequence: 0, 1, 2, 3. A second set of four pages, after plane interleaving, are written in the following sequent: 7, 4, 5, 6. After writing the data, the pages of written data are read, page swapped if necessary, and then written into another portion of memory (such as MLC).