SRAM Sense Margin Improvement via Lower Threshold Voltage Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory devices face challenges in maintaining a sufficient sense margin due to process variations and power constraints, which can lead to inaccurate read operations, especially in smaller devices, and column multiplexers like CMOS degrade the sense margin while pMOS multiplexers reduce voltage, affecting performance.
Innovation Solution
The implementation of lower threshold voltage transistors in pMOS column multiplexers, fabricated using the same mask as other components, increases the sense margin without degrading voltage, and a keeper circuit aids in maintaining voltage levels at the sense amplifier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If pMOS column multiplexers are used to avoid CMOS drawbacks, then area and bit line capacitance are improved, but voltage in bit lines decreases reducing sense margin
Solution Approach 1:
The patent changes the threshold voltage parameter of the pMOS transistors in the column multiplexer from standard to lower threshold voltage. This parameter change allows the multiplexer to maintain higher bit line voltages while still providing the necessary switching function, thereby resolving the contradiction between using pMOS multiplexers and maintaining sense margin.
2Reliability
If timing is delayed to increase sense margin, then sense margin is improved, but access time increases degrading overall performance
Solution Approach 1:
Instead of delaying timing to improve sense margin, the patent changes the transistor threshold voltage parameter to achieve both goals simultaneously. The lower threshold voltage pMOS transistors provide higher bit line voltages that improve sense margin while maintaining fast switching speeds, eliminating the need for timing delays and preserving access time performance.
3Productivity
If smaller memory devices are implemented, then density is improved, but process variation increases making sense margin insufficient
Solution Approach 1:
The patent applies parameter changes to the column multiplexer transistor threshold voltage to compensate for increased process variations in smaller memory devices. By using lower threshold voltage transistors, the bit line voltage levels are maintained at higher levels despite process variations, ensuring sufficient sense margin even in densely packed smaller memory devices.
Data Source
AI summary
A sense margin is improved for a read path in a memory array. Embodiments improve the sense margin by using gates with a lower threshold voltage in a read column multiplexer. A cross coupled keeper can further improve the sense margin by increasing a voltage level on a bit line storing a high value, thereby counteracting leakage on the “high” bit line.