Flash Memory Voltage Adjustment for Read Reliability
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Solution Overview
Problem
As the number of programming/erasing cycles increases in flash memory devices, memory cell degradation reduces the current flowing through memory cells, leading to unreliable reading operations, especially when the selected memory cell is the worst on-cell, causing a decrease in current flow and precharging voltage discharge issues.
Innovation Solution
A flash memory device comprising a memory cell array, a voltage generator, a row selection circuit, and a control logic circuit that generates selection and non-selection voltages based on the location of a selected memory cell, adjusting the voltages to minimize source resistance and enhance current flow by varying the first and second non-selection voltages accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of programming/erasing cycles increases, then the memory device can store more data, but the programming characteristics of memory cells degrade and current flow decreases
Solution Approach 1:
The patent applies parameter changes by adjusting the voltage levels applied to non-selected word lines based on the position of the selected word line. Specifically, different voltage levels (first voltage level for word lines closer to the selected line, second voltage level for word lines farther away) are used to compensate for the increased source resistance caused by memory cell degradation from repeated programming/erasing cycles, thereby maintaining reliable reading operations despite extended usage.
2Productivity
If memory cells coupled to non-selected word lines are turned on during reading, then the reading operation can proceed, but source resistance increases and current flow through the selected memory cell decreases
Solution Approach 1:
The patent applies local quality by differentiating the voltage treatment of non-selected word lines based on their spatial relationship to the selected word line. Word lines closer to the selected line receive a first voltage level that maintains lower resistance, while word lines farther away receive a second voltage level. This localized voltage adjustment compensates for the position-dependent source resistance effect, ensuring sufficient current flow reaches the selected memory cell even when multiple non-selected cells are turned on for parallel reading operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the reliability of reading operations by increasing current flow through the selected memory cell, ensuring timely discharge of the bit-line precharging voltage and reducing read disturbance, thereby enhancing the overall performance of the flash memory device.
Implementation Method 1
turning on the memory cells coupled to non-selected word lines causes the memory cells to have resistance. The resistance impacts the current flowing though the cell string
Implementation Method 2
A memory cell in NAND flash memory may be erased or programmed using Fowler-Nordheim (F-N) tunneling current
Data Source
AI summary
Disclosed is a flash memory device including a memory cell array having memory cells arranged at intersections of word lines and bit lines, such that one bit line is associated with a plurality of memory cells connected in series, a voltage generator configured to generate at least a first selection voltage, a row selection circuit configured to drive the non-selected word lines based on at least the first non-selected voltage, and a control logic circuit configured to control the voltage generator and the row selection circuit, such that the voltage generator generates at least the first non-selection voltage based on a location of a selected memory cell in the plurality of memory cells.