Semiconductor Memory Device Flag Cell Read Voltage Control

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Solution Overview

Problem

In NAND flash memory, the storage of multi-valued data using flag cells is challenged by the inability to correctly read user data when the threshold voltage of flag cells decreases, leading to incorrect determination of data states, particularly between the states before and after writing the upper page, resulting in improper data retrieval.

Innovation Solution

A semiconductor memory device with a memory cell array and control circuit that uses different read voltages to determine data stored in memory cells and flag cells, allowing for accurate identification of data states by supplying specific read voltages to word lines and using sense amplifiers to latch and output data based on these determinations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single read voltage is used to read data from memory cells and flag cells, then the read operation is simple and fast, but the threshold voltage decrease in flag cells causes incorrect determination of data states

Engineering Contradiction:
Improveaccuracy of data state determinationVSAvoidread operation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by using different read voltages for flag cells and memory cells. Specifically, a first read voltage is applied to the flag cell and a second read voltage (different from the first) is applied to the memory cell during the read operation. This voltage differentiation allows the system to accurately determine the state of both the flag cell and the memory cell even when threshold voltage degradation occurs, thereby resolving the contradiction between reliable data state determination and operational simplicity.

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If multi-valued data is stored using flag cells to determine upper page write status, then data storage capacity is increased, but incorrect reading occurs when flag cell threshold voltage decreases

Engineering Contradiction:
Improvedata storage capacityVSAvoidread accuracy of flag cell state
Core Design Contradiction:
Quantity of substanceVSMeasurement precision

Solution Approach 1:

The patent resolves the measurement precision issue by changing the electrical parameter (voltage) used to read the flag cell. A first read voltage specifically tailored for the flag cell is applied, which accounts for the threshold voltage characteristics and degradation of the flag cell. This ensures that even as the flag cell's threshold voltage decreases over time or due to interference, the read operation can still accurately determine whether the upper page has been written, thereby maintaining high read accuracy while preserving the increased data storage capacity enabled by multi-valued storage.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If different read voltages are applied to flag cells and memory cells, then accurate data state determination is achieved, but the read operation time increases

Engineering Contradiction:
Improveaccuracy of data readingVSAvoidread operation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing the flag cell read operation before the memory cell read operation. The control circuit first determines the state of the flag cell using the first read voltage, and based on this result, it then determines the state of the memory cell using the second read voltage. This sequential approach with preliminary flag cell assessment allows the system to optimize the overall read process, ensuring accurate data state determination while minimizing total read time by avoiding unnecessary operations and enabling early termination or optimization based on flag cell state.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8867269B2Semiconductor memory device
Publication Date: 2014.10.21 KIOXIA CORP
  • US8867269B2 patent drawing
  • US8867269B2 patent drawing
  • US8867269B2 patent drawing

AI summary

A semiconductor memory device includes: a memory cell array including a plurality of memory cells, a plurality of word lines, and a plurality of bit lines, and a control circuit. A first memory cell stores first data of n bits, a second memory cell stores second data used to determine whether data of k bits is stored in the first memory cell, and the control circuit performs first determination of determining data read from the data of the second memory cell, performs second determination of determining data read from the second memory cell by supplying the first word line with a second read voltage different from the first read voltage, and outputs either one of a result obtained by reading the data stored in the first memory cell at the first read voltage and a result obtained by reading the data stored in the first memory cell at the second read voltage, based on a result of the second determination.