Adaptive Frequency Scaling for CPU and Bus Power Optimization
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Solution Overview
Problem
Dynamic Voltage and Frequency Scaling (DVFS) technologies primarily focus on CPU power reduction, neglecting the impact on system performance due to independent bus activity, leading to restricted power reduction and performance issues in digital systems.
Innovation Solution
An Adaptive Frequency Scaling (AFS) system that includes a controller to dynamically adjust both CPU and bus clock frequencies based on operation information from the CPU, bus, and function blocks, ensuring synchronized frequency changes to maintain system performance and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If DVFS technology changes only CPU clock frequency based on CPU operation information, then CPU power consumption is reduced, but system performance deteriorates due to independent bus activity
Solution Approach 1:
The patent segments the frequency scaling approach by independently controlling CPU clock frequency and bus clock frequency based on their respective operation information. The AFS controller separately determines frequency changes for CPU and bus, allowing each component to be optimized independently rather than treating them as a single unit, thus resolving the contradiction between CPU power reduction and system performance maintenance
Solution Approach 2:
The patent implements dynamic frequency scaling for both CPU and bus components. The AFS controller dynamically adjusts CPU clock frequency based on CPU operation information and bus clock frequency based on bus operation information, enabling the system to adapt to varying workload conditions and maintain optimal performance while reducing power consumption
2Productivity
If DVFS technology changes only CPU clock frequency, then CPU operation is optimized, but power reduction range is restricted
Solution Approach 1:
The AFS controller serves multiple functions by simultaneously managing both CPU frequency scaling and bus frequency scaling. It determines frequency changes for both components based on their respective operation information, making the frequency scaling mechanism universally applicable to the entire system rather than limited to CPU operations alone, thereby expanding the overall power reduction range
3Speed
If bus clock frequency is increased independently, then bus throughput is improved, but CPU frequency must be increased proportionally to maintain synchronization
Solution Approach 1:
The AFS controller uses feedback from operation information of both CPU and bus to determine appropriate frequency changes. It receives operation information from both components, processes this feedback, and coordinates frequency adjustments accordingly, simplifying the complexity of maintaining synchronization between CPU and bus frequencies through intelligent control
Data Source
AI summary
An apparatus and method for adaptively changing clock frequencies of a Central Processing Unit (CPU) and a bus in a digital system are provided. The system includes an Adaptive Frequency Scaling (AFS) controller and a clock controller. The AFS controller determines whether to change a clock frequency of the CPU according to operation information of the CPU, and determines whether to change a clock frequency of the bus according to operation information of the bus. The clock controller generates a clock frequency of the CPU and a clock frequency of the bus according to the determination of the AFS controller.