Energy Efficient ICT TRIZ Cases

A cache memory system uses delayed-replacement information to manage texture data storage in tile-based rendering environments.

R-WSLP protocol employs distributed TDMA and linear configuration to minimize idle listening and reduce network latency in large-scale sensor networks.

A distributed task processing apparatus selects tasks based on control parameters to enable independent unit scheduling.

Extracts cross-power spectral density phase slope to synchronize time-domain signals despite varying sampling rates and unsynchronized clocks.

Slave devices arbitrate data values on a multiple-access bus to determine an extreme value, reducing the number of required transactions and power consumption.

A network interface controller maps packets to processors using hash indirection tables.

A power management system controls electronic device elements by prioritizing power consumption against a defined draw limit.

Dynamic processor switching manages light source power consumption while maintaining screen luminance during static and active display states.

A circuit monitors an SPI select signal to transition between active and reduced power states without extra hardware.

A pattern detection engine analyzes modulated light signals from an optical finger navigation sensor to distinguish intentional movement from ambient interference.

A virtualized environment power conservation module assigns virtual machines to physical hosts using real-time power data.

Buffer circuits isolate memory chips from the data bus, reducing electrical load and enabling higher operation frequency.

A switching circuit dynamically selects host clock signals from dual phase-locked loops to adjust front side bus frequency.

The adaptive frequency scaling controller synchronizes CPU and bus clock adjustments to overcome performance bottlenecks caused by independent DVFS technologies.

A hypervisor schedules periodic tasks from multiple operating systems onto a single processor core.

A secure real-time clock system uses a frequency divider to adjust the clock line signal.

A method stores running data of a first operating system in a dump area before loading a second operating system into system memory.

A single external power supply feeds local voltage regulators that adjust logic block voltages based on operational needs.

A storage management apparatus prioritizes logical volume activation to optimize power supply unit usage.

Hardware power control registers set operating states for functional blocks, eliminating software-based distribution errors and reducing power consumption.

A semiconductor chip uses integrated temperature sensors and a power manager to adjust operating parameters based on measured thermal conditions.

An interrupt message circuit generates set and clear signals for level-sensitive delivery over a communication fabric.

Delaying pending processor instructions elongates idle intervals to enable effective power gating activation.

A signal spreader circuit spaces out concurrent interrupts via preliminary action, suppressing in-rush currents that cause operational malfunctions.

A unified framework blends two-stage Kalman filtering with augmented Savitzky-Golay smoothing to process SCADA measurements.

A vehicle communication system adjusts channel scan frequency based on engine status and movement rate to optimize connection attempts.

A portable electronic device transmits screen control information to an external display unit for direct user interaction.

Master cache uses line identification values to store retrieved data directly, eliminating address buffer queues that limit parallel request throughput.

Firmware monitors error thresholds and bus counters to adjust PCIe endpoint speeds, resolving bandwidth bottlenecks when total demand exceeds capacity.

A communication apparatus modifies transmitted frames to distribute conversations across multiple links.

A base station maps device group identifiers to common identifiers for multicast transmission.

Segmented memory domains and intermediary buffers maintain fast access times and reliability while reducing idle power consumption.

Dynamic workload reallocation across heterogeneous processing components in a multi-processor system on a chip.

A control circuit dynamically gates the clock signal for an asynchronous data bus interface.

A management device allocates workloads across information processing units to minimize total power consumption.

A hibernation mode preserves active states in non-volatile storage while cutting power to volatile memory.

A portable device power management system detects nearby wireless charging devices to present timely notifications before critical power depletion.

Slave devices count frame synchronization signals to determine time slots, eliminating master logic and reducing system complexity.

An adaptive modulation control system corrects propagation path information using measured reception states to select appropriate modulation parameters.

A memory controller tracks read and write requests to throttle external memory access based on a bank counter threshold.

Time shared memory access divides cycles into slots to resolve inflexible configurations and suboptimal performance in computer systems.

A diagnostic process classifies MODBUS server devices as operational or malfunctioning to manage transaction participation.

A network node suppresses interrupts to reduce processor power consumption.

A storage system reduces power by shortening disk seek distances through sweep scheduling and request deferral.

A mobile station monitors a single paging block index for multiple subscriber identities to consolidate network signaling tasks.

A Southbridge generates a dedicated CPU reset signal to directly control processor state without triggering full system re-initialization.

A non-volatile storage unit checks memory accessibility to enable immediate processor power shutdown.

A virtual machine monitor selects between busy wait and blocking methods to manage processor scheduling.