Registered DIMM Data Bus Buffering for Electrical Load Reduction
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Solution Overview
Problem
Conventional registered Dual In-line Memory Modules (DIMM) systems are limited by high electrical loading on the data bus, which restricts memory capacity and operation frequency, allowing only two DIMM modules per memory channel.
Innovation Solution
The introduction of Data Bus Buffers/Switches on the DIMM module to reduce electrical loading by buffering and driving the data bus, controlled by a CMD/CTRL Buffer for command and control signals, allowing multiple DIMM modules to be connected to a common bus, thereby increasing memory capacity and access speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If memory chips are connected directly to the data bus, then the system structure is simple, but the electrical loading on the data bus becomes too high, limiting memory capacity and operation frequency
Solution Approach 1:
A buffer circuit is introduced as an intermediary component between the data bus and memory chips. The buffer receives data from the data bus and distributes it to multiple memory chips, reducing the electrical loading on the data bus while enabling connections to more memory chips, thus increasing memory capacity without excessive complexity increase
Solution Approach 2:
The data bus connection is segmented into multiple parallel paths through the buffer circuit, which can simultaneously drive multiple memory chips. This segmentation allows the data bus to serve more memory chips without the electrical load on any single path becoming excessive, enabling higher memory capacity
2Device complexity
If memory chips are connected directly to the data bus, then the device complexity is low, but the operation frequency is limited due to high electrical loading
Solution Approach 1:
The buffer circuit acts as a mediator that isolates the high-frequency data bus from the memory chips, allowing the bus to operate at higher frequencies without being burdened by the total load of all memory chips. The buffer handles the driving burden, enabling increased operation frequency with minimal complexity increase
Solution Approach 2:
The buffer circuit changes the electrical parameters (impedance, loading) between the data bus and memory chips, creating a more favorable electrical environment for high-frequency operation by reducing the effective load on the bus while maintaining connectivity to multiple chips
3Quantity of substance
If only two DIMM modules are connected per memory channel, then the electrical loading is manageable, but the memory capacity is limited
Solution Approach 1:
The buffer circuit on each DIMM module serves as an intermediary that manages electrical loading locally. By buffering the data bus connections, it allows more DIMM modules to be connected to the memory channel while keeping the electrical loading on each individual module and the shared bus within manageable levels, thus increasing total memory capacity
Solution Approach 2:
The solution moves from a one-to-one or one-to-two connection model to a one-to-many connection model by introducing the buffer circuit. This dimensional change in connection topology allows multiple DIMM modules to share the data bus efficiently, increasing capacity without proportionally increasing electrical loading issues
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables higher memory capacity and faster access speeds by reducing the electrical load on the memory controller, allowing more than two DIMM modules to be connected per channel, thereby enhancing the overall performance of the memory system.
Implementation Method 1
the data bus is buffered on the DIMM
Implementation Method 2
an electrical load reduction circuit coupled between the electrical contacts and the memory chips to write data received from the data bus into the memory chips or to read data from the memory chips onto the data bus, an electrical load of the memory chips on the data bus being smaller with the memory chips being coupled to the data bus via the electrical load reduction circuit
Data Source
AI summary
A Registered DIMM (RDIMM) system with reduced electrical loading on the data bus for increases memory capacity and operation frequency. In one embodiment, the data bus is buffered on the DIMM. In another embodiment, the data bus is selectively coupled to a group of memory chips via switches.