Network Interface Controller Packet Distribution for Processor Contention

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Solution Overview

Problem

In multi-processor systems, contention issues arise when multiple processors attempt to access shared connection state data for network packets, leading to delays due to the need for data locking.

Innovation Solution

A network interface controller (NIC) maps packets to specific processors based on their flow tuple, using hash operations and indirection tables to distribute packets efficiently and adapt the number of processors handling flows in response to changing network traffic, thereby reducing contention and optimizing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple processors handle packets for the same connection, then processing capacity increases, but processor contention increases due to shared state data access

Engineering Contradiction:
Improveprocessing capacityVSAvoidprocessor contention delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments connection state data into separate cache lines allocated to different processors. When a connection is hashed to a primary processor, that processor gets exclusive access to the corresponding cache lines, preventing other processors from accessing the same state data even if they are handling packets for the same connection. This segmentation eliminates contention while allowing multiple processors to handle packets.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements local quality by allowing each processor to have its own local cache memory with dedicated cache lines for connection state data. Each processor's cache is optimized for its assigned connections, providing fast local access without needing to access shared memory. This local optimization resolves the contradiction by enabling each processor to independently handle packets for its assigned connections without contention.

Inventive Principle:
Principle #3Local quality

2Productivity

If more processors are activated to handle increased network traffic, then processing capacity increases, but power consumption increases

Engineering Contradiction:
Improveprocessing capacityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic processor activation and deactivation based on network traffic conditions. The NIC monitors traffic load and dynamically adjusts which processors are active, hashing connections to available processors. When traffic decreases, processors can be deactivated or put into low-power states, reducing power consumption while maintaining the ability to handle traffic spikes by activating processors as needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent makes the processor set universal by allowing any available processor to handle any connection based on hash mapping. Instead of dedicating specific processors to specific connections, any processor can handle any connection if it is active and has the necessary cache lines allocated. This universality allows flexible activation/deactivation of processors based on traffic conditions, optimizing power consumption while maintaining processing capacity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of operation

If connection state data is stored in shared memory, then accessibility improves, but access speed decreases due to locking requirements

Engineering Contradiction:
Improvedata accessibilityVSAvoidstate data access speed
Core Design Contradiction:
Ease of operationVSSpeed

Solution Approach 1:

The patent segments shared connection state data into separate cache lines that are exclusively allocated to specific processors based on hash mapping. Instead of having all processors access the same shared memory locations with locking, each processor gets dedicated cache lines for its assigned connections. This segmentation provides both fast local access (improving speed) and maintains accessibility (improving ease of operation) because each processor has direct access to its allocated cache lines without contention.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces cache memory as an intermediary between processors and main memory for storing connection state data. The cache acts as a local buffer that processors can access quickly without needing to access shared memory with locking. The hash-based allocation mechanism mediates which processor gets which cache lines, providing fast access while maintaining system-wide accessibility through the cache hierarchy.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8031612B2Altering operation of a network interface controller based on network traffic
Publication Date: 2011.10.04 TAHOE RES LTD
  • US8031612B2 patent drawing
  • US8031612B2 patent drawing
  • US8031612B2 patent drawing

AI summary

A method includes, at a network interface controller receiving packets from a network connection for a set of multiple coupled processors, distributing received packets to each of a first set of the processors. In response to determining the change in network traffic, operation of the network interface controller is altered to distribute packets to a second set of the processors.