Interrupt Suppression Strategy for Network Processor Power

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Solution Overview

Problem

Existing techniques for interrupting processors in computer systems are inefficient, particularly on busy networks, as they either lead to high power consumption or degrade performance due to unnecessary processor wake-ups for irrelevant packets, and conventional methods to reduce interrupts either fail to save energy or adversely affect time-sensitive packets.

Innovation Solution

A system that suppresses interrupts by transmitting a first interrupt to the processor upon receiving a packet, enabling an interrupt-suppression state, and re-enabling it only when a pre-specified threshold, such as a time interval or buffer occupancy, is met, allowing for prompt processing of packets while reducing overall interrupt frequency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If interrupts are transmitted for every received packet, then packet processing timeliness is improved, but processor power consumption increases

Engineering Contradiction:

Improvepacket processing delayVSAvoidprocessor power consumption

Core Design Contradiction:

Loss of timeVSUse of energy by moving object

Solution Approach 1:

The patent implements periodic interrupt suppression where the network interface controller transmits interrupts to the processor at periodic intervals rather than for every single packet. This allows the processor to remain in low-power states during intervals without missing critical packets, thereby reducing power consumption while maintaining acceptable processing timeliness.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The network interface controller performs preliminary filtering and buffering of packets before transmitting interrupts to the processor. By pre-processing packets and grouping them into batches, the controller reduces the frequency of processor wake-ups while ensuring packets are ready for immediate processing when the processor becomes available, thus addressing both power consumption and timeliness concerns.

Inventive Principle:

Principle #10Preliminary action

2Use of energy by moving object

If interrupt suppression delay is implemented to reduce interrupts, then power consumption is reduced, but time-sensitive packet handling deteriorates

Engineering Contradiction:

Improveprocessor power consumptionVSAvoidtime-sensitive packet processing time

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent applies different interrupt suppression strategies to different types of packets based on their characteristics. Time-sensitive packets (such as those with high priority or specific protocols) are handled with shorter suppression delays or immediate interrupt transmission, while non-time-sensitive packets use longer suppression intervals. This localized differentiation ensures time-sensitive packets are processed promptly while still achieving power savings for other traffic.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The interrupt suppression mechanism dynamically adjusts its parameters based on network conditions, packet types, and processor workload. The suppression delay duration is not fixed but adapts according to the urgency and importance of incoming packets, allowing the system to optimize between power consumption and processing timeliness in real-time based on actual traffic patterns.

Inventive Principle:

Principle #15Dynamics

3Productivity

If interrupt suppression is used to batch packets, then interrupt frequency is reduced, but overall system performance degrades due to waiting

Engineering Contradiction:

Improveinterrupt processing efficiencyVSAvoidnetwork operation completion time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The network interface controller acts as an intermediary between the network and processor, performing packet batching, filtering, and pre-processing functions. By grouping multiple packets into single interrupt transmissions and performing preliminary processing in the controller, the system reduces the total number of processor interruptions while maintaining efficient throughput, thus improving overall productivity without significant performance loss.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS9542345B2Interrupt suppression strategy

Publication Date: 2017.01.10 APPLE INC

AI summary

The disclosed embodiments provide a system that suppresses interrupts to facilitate efficient use of a processor in a computer system. The system includes a node that transmits a first interrupt to the processor upon receiving a first packet for processing at the processor and disables subsequent interrupts to the processor during an interrupt-suppression state in the processor. The system also includes the processor, which processes the first packet upon receiving the first interrupt and transmits a first acknowledgment of the first packet to the node to enable the interrupt-suppression state.