Time Shared Memory Access for Flexible Allocation
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Solution Overview
Problem
Existing memory configurations in computer systems are inflexible and inefficient, requiring prior knowledge of application sizes and transfer requirements, leading to compromises that result in suboptimal performance and energy usage, especially when instruction RAM is insufficient or data buffer memory is too small.
Innovation Solution
A single SRAM device accessible by both CPU and memory busses, utilizing time-shared access with separate clock frequencies, allowing dynamic allocation and efficient data transfer by receiving a base clock signal that combines CPU and system clock frequencies, enabling zero wait access times and flexible memory allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single memory device is accessed by multiple masters using different clocks, then memory flexibility and allocation efficiency are improved, but clock synchronization and access coordination become more complex
Solution Approach 1:
The patent implements time-shared access by dividing the memory access cycle into periodic time slots, where each master (CPU or memory bus) is granted exclusive access during its designated time slot. The memory device alternates between serving CPU requests and memory bus requests in a periodic manner, synchronized by a base clock that runs at least as fast as the sum of the CPU clock and memory bus clock frequencies. This periodic time-division multiplexing allows flexible memory allocation to different masters without requiring complex simultaneous arbitration logic.
2Productivity
If memory size is increased to handle larger data transfers, then data transfer capability is improved, but memory cost and system resource usage increase
Solution Approach 1:
The patent makes the memory device universal by enabling it to serve multiple functions and multiple masters. The same memory resource is dynamically allocated to different masters (CPU or memory bus) depending on current system needs. During CPU instruction execution, the memory serves as instruction RAM; during data transfer operations, the same memory serves as data buffer. This multi-functionality eliminates the need for separate dedicated memory resources for each function, improving data transfer capability without proportionally increasing total memory size.
3Speed
If separate instruction RAM and data buffer memories are used, then access speed is improved, but system complexity and memory allocation flexibility worsen
Solution Approach 1:
The patent merges the previously separate instruction RAM and data buffer into a single unified memory device. This single memory is accessible by both the CPU and memory bus through time-shared access. The CPU can access instructions during its clock cycles while the memory bus accesses data during its clock cycles, with the memory switching between masters based on time-division multiplexing controlled by the base clock. This merging reduces the number of separate memory components while maintaining access speed through synchronized time-shared operation.
Data Source
AI summary
Apparatus and method are provided for accessing information in a storage area including a storage area which is accessible by a first buss and a second buss. The access by the first buss is clocked by a first clock signal and the access by the second buss is clocked by a second clock signal. The first clock signal has a first clock frequency and the second clock signal has a second clock frequency. A terminal receives a base clock signal having a frequency of at least the sum of the first clock frequency and the second clock frequency. An access to the storage area by the first or second buss is made during a cycle of the base clock.