Processor Instruction Delay for Power Gating
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Solution Overview
Problem
Existing power-saving techniques in computer systems, such as power gating and transparent clock gating, are inefficient due to short idle periods, which do not sufficiently utilize the overhead associated with activating and deactivating these techniques, despite a large fraction of idle cycles.
Innovation Solution
The method involves delaying the execution of non-critical instructions and pending off-chip memory requests to elongate idle periods, allowing for increased application of power-saving techniques like power gating and clock gating, thereby enhancing power savings without significant performance overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power gating or transparent clock gating is applied during idle periods, then power consumption is reduced, but the short duration of idle periods makes the activation/deactivation overhead significant
Solution Approach 1:
The system performs preliminary actions by delaying the issuance of ready instructions and pending memory requests before entering power savings mode. This allows the system to accumulate enough idle cycles to justify the overhead of activating power gating or transparent clock gating, ensuring that the power savings technique can be effectively applied.
Solution Approach 2:
The system dynamically adjusts the issuance of instructions and memory requests based on the current idle period characteristics. By making the instruction issuance dynamic rather than static, the system can elongate idle periods when beneficial for power savings while maintaining performance when idle periods are too short to justify power savings mode activation.
2Loss of energy
If instructions are delayed to elongate idle periods, then power savings potential increases, but execution time may be extended
Solution Approach 1:
The system uses its own ready instructions and pending memory requests as the source of delay candidates. By selectively delaying instructions that are already ready or pending, the system creates idle periods without requiring external resources or adding complex external control mechanisms.
Solution Approach 2:
The system changes the timing parameters of instruction issuance and memory request timing to elongate idle periods. By adjusting when instructions are issued and when memory requests are sent, the system can create longer continuous idle periods that make power savings techniques more effective, while managing the overall execution time impact.
Data Source
AI summary
Embodiments relate to storing data in memory. An aspect includes applying a power savings technique to at least a subset of a processor. Pending work items scheduled to be executed by the processor are monitored. The pending work items are grouped based on the power savings technique. The grouping includes delaying a scheduled execution time of at least one of the pending work items to increase an overall number of clock cycles that the power savings technique is applied to the processor. It is determined that an execution criteria has been met. The pending work items are executed based on the execution criteria being met and the grouping.