Switching Circuit for Dynamic Front Side Bus Clock Frequency Adjustment
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Solution Overview
Problem
Current methods for adjusting the operating frequency of the front side bus in portable computers are inconvenient, requiring repeated rebooting and affecting normal operation, leading to inefficient power management and performance enhancement.
Innovation Solution
A switching circuit and method that dynamically switches host clock signals by generating a new host clock signal when the CPU enters a sleep state, allowing the front side bus to adjust its operating frequency without rebooting, using phase-locked loops to stabilize the frequency adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the operating frequency of the front side bus is adjusted by changing BIOS configuration at computer startup, then the operating frequency can be adjusted, but the computer requires repeated rebooting which is inconvenient to users
Solution Approach 1:
The patent generates a new host clock signal in advance when the CPU enters sleep state, before the frequency adjustment is needed. This preliminary preparation allows the frequency change to take effect immediately when the CPU resumes operation, eliminating the need for rebooting and making the adjustment convenient for users.
Solution Approach 2:
The patent enables dynamic frequency adjustment during CPU operation by utilizing the sleep state transition. The frequency can be changed from 166 MHz to 100 MHz or other values without requiring system reboot, making the adjustment process dynamic and user-friendly while maintaining system stability.
2Ease of operation
If the operating frequency of the front side bus is adjusted dynamically during operation, then frequency can be changed without rebooting, but normal operation of the front side bus is affected causing computer to crash easily
Solution Approach 1:
The patent generates the new host clock signal in advance when the CPU enters sleep state, before any frequency adjustment operation is performed. This ensures that the frequency change is prepared and ready to take effect immediately upon CPU resumption, avoiding disruption to normal operation and preventing system crashes.
Solution Approach 2:
The patent uses the CPU sleep state as an intermediary condition to facilitate frequency adjustment. By transitioning the CPU to sleep state temporarily, the system can change the host clock signal without affecting the front side bus operation, thus maintaining reliability while enabling dynamic adjustment.
3Adaptability or versatility
If small-ranged frequency adjustments are made repeatedly to achieve substantial frequency change, then the front side bus frequency can be adjusted, but the adjustment process becomes complex and efficiency is low
Solution Approach 1:
The patent generates the target frequency host clock signal in advance during CPU sleep state, before the frequency adjustment is needed. This allows substantial frequency changes (e.g., from 166 MHz to 100 MHz or other values) to be implemented in a single operation rather than requiring multiple small steps, dramatically improving adjustment efficiency.
Solution Approach 2:
The patent creates a copy of the host clock signal at the desired frequency during CPU sleep state. This copied signal is then switched to replace the original signal when the CPU resumes operation, enabling direct substitution of frequency values without iterative adjustment and significantly improving productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables convenient and efficient adjustment of the front side bus frequency, reducing power consumption and enhancing performance without disrupting normal operations, allowing for dynamic frequency adjustments based on usage conditions.
Implementation Method 1
using phase-locked loops to stabilize the frequency adjustments
Data Source
AI summary
A switching circuit located in a computer system is disclosed in the present invention. The switching circuit comprises a first phase-locked loop generating a first host clock signal, a second phase-locked loop generating a second host clock signal and an output switch unit coupled to the first PLL and the second PLL. When the computer system operates in a first mode, the output switch unit chooses the first host clock signal to be a fundamental clock signal of the front side bus. In the other hand, when the computer system operates in a second mode, the output switch unit chooses the second host clock signal to be a fundamental clock signal of the front side bus.