Race-Free Level-Sensitive Interrupt Delivery via Fabric
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In computing systems, peripherals asserting interrupts can create a race condition between write operations and interrupt service routine execution, leading to erroneous operations due to data not being globally visible when read by the CPU.
Innovation Solution
An interrupt message circuit is introduced to ensure that write operations are globally visible before transmitting interrupt messages over a communication fabric, alleviating the race condition by tracking and ordering operations, and using level-sensitive interrupt signals with set and clear messages to maintain accurate interrupt states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If interrupts are delivered immediately after peripheral write operations, then interrupt response time is improved, but race conditions occur where data is not globally visible causing erroneous operations
Solution Approach 1:
The interrupt message circuit performs preliminary action by tracking write operations and ensuring they are globally visible before transmitting the interrupt message. The circuit waits for write completion and visibility confirmation before asserting the interrupt, eliminating the race condition while maintaining timely interrupt delivery.
2Reliability
If write operations are tracked to ensure global visibility, then data integrity is improved, but device complexity increases due to additional tracking circuitry
Solution Approach 1:
The interrupt message circuit merges multiple functions into a single integrated component: it tracks write operations, determines global visibility, and transmits interrupt messages. By combining these functions in one circuit rather than separate components, the solution achieves data integrity without proportionally increasing overall device complexity.
3Reliability
If interrupt messages are transmitted on communication fabric after write operations, then race conditions are alleviated, but transmission time is increased
Solution Approach 1:
The interrupt message circuit operates continuously, tracking write operations and preparing interrupt messages in parallel. Rather than sequential processing, the circuit maintains continuous monitoring and transmission readiness, minimizing the delay between write completion and interrupt delivery while ensuring correct ordering.
Data Source
AI summary
In an embodiment, a system includes at least one peripheral device, an interrupt controller, a memory controller, at least one CPU, and an interrupt message circuit coupled to the peripheral device. The interrupt message circuit may be coupled to receive the interrupt signal from the peripheral device, and may be configured to generate an interrupt message for transmission on a communication fabric. In some embodiments, there may be multiple peripherals which have independent paths through the fabric for memory operations to the memory controller. Each such peripheral may be coupled to an instance of the interrupt message circuit. In an embodiment, the interrupt is level sensitive. The interrupt message circuit may be configured to transmit interrupt set messages an interrupt clear messages to the interrupt controller, to indicate the levels.