Asynchronous Data Bus Interface Clock Control
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Solution Overview
Problem
The integration of asynchronous data interfaces in synchronous integrated circuits poses timing challenges and increases power consumption due to unnecessary digital noise, as existing design tools are primarily suited for synchronous logic, leading to inefficiencies and interference in RF signal processing circuits.
Innovation Solution
A data bus interface circuit that dynamically provides a clock signal only when needed, using a control circuit and logic AND gate to detect data transmission states and apply the clock signal during communication, then shut it off after transmission, allowing for manual implementation without extensive design efforts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock signal is continuously provided to the interface circuit, then the interface can be ready to receive data immediately, but power consumption increases and digital noise is generated even when the interface is not in use
Solution Approach 1:
The patent applies the dynamics principle by making the clock signal dynamic rather than static. The clock signal is enabled only during active data transmission periods and disabled during idle periods. This is achieved through a control circuit that detects data transmission states and dynamically controls the clock signal routing via AND gates, allowing the system to adapt its operational state to match actual data communication needs, thereby reducing power consumption while maintaining interface readiness when required.
2Reliability
If a clock signal is continuously provided to the interface circuit, then the interface operates reliably, but digital noise increases interfering with RF signal processing
Solution Approach 1:
The patent applies the extraction principle by separating the clock signal provision into distinct operational phases. The continuous clock signal is extracted and replaced with a conditional clock signal that is only provided when data transmission is detected. The control circuit extracts the necessary clocking function only during active communication periods, removing the harmful continuous clock signal that generates digital noise during idle periods, thus protecting sensitive RF signal processing from interference.
3Use of energy by moving object
If the clock signal is switched off when not in use, then power consumption is reduced, but the interface may miss externally initiated connection setup
Solution Approach 1:
The patent applies the preliminary action principle by implementing a control circuit that continuously monitors the data and clock lines for start conditions even when the interface clock is disabled. The control circuit performs preliminary detection of externally initiated connections by scanning the interface lines for specific state combinations indicating data transmission beginning. When a start condition is detected, the control circuit immediately enables the clock signal and activates the interface circuit, ensuring no connection setup is missed while maintaining power savings during idle periods.
Data Source
AI summary
In a data bus with asynchronous data transmission via a clock and a data line, the transmitted data are ascertained by sampling with a multiple of the data rate of the data bus. Sampling is done in this case with a clock which is not synchronous with the asynchronous clock of the data bus. For avoiding interferences which develop due to the unnecessary operation of the interface circuit with a high frequency clock when no data are currently transmitted, a control circuit is provided for detecting the beginning and the end of a data transmission. Only at the beginning of a data transmission, the interface circuit will be supplied with the required clock. After the end of the data transmission, the clock for the interface circuit will be switched off again. The control circuit is preferably designed as a state machine which reacts, without the need for clock signals, to the states on the data and clock line of the data bus.