Southbridge CPU Reset Signal Path
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Solution Overview
Problem
Conventional CPU reset methods require a complete system reset, leading to unnecessary initialization and data loss in the Northbridge registers, increasing complexity and cost, especially when transitioning from power-saving modes.
Innovation Solution
A method where the Southbridge delivers a CPU reset signal to the Northbridge, which relays it to the processor, allowing individual CPU resets without affecting other system units, and using sideband pins to provide startup options like frequency ratios, with data backup and restoration to prevent initialization and data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a complete system reset is performed to reset the processor, then the processor reset is achieved, but the Northbridge and Southbridge are also reset causing data loss and requiring initialization
Solution Approach 1:
The patent segments the reset function by creating a dedicated CPU reset signal path that is separate from the system reset path. The Southbridge generates a CPU_RST# signal specifically for the processor, while the Northbridge can be excluded from this reset operation. This segmentation allows selective resetting of only the processor without affecting other system components, thereby preventing data loss in the Northbridge registers while ensuring reliable processor reset.
2Reliability
If a complete system reset is performed to reset the processor, then the processor reset is achieved, but system complexity and initialization requirements increase
Solution Approach 1:
The patent divides the reset control into separate segments: a system reset function handled by the Northbridge and a CPU-specific reset function handled by the Southbridge. By implementing a dedicated CPU reset signal path, the system avoids the complexity of complete system initialization when only processor reset is needed. This segmentation simplifies the overall system architecture by providing granular control over reset operations.
Solution Approach 2:
The Southbridge acts as an intermediary device that generates and controls the CPU reset signal independently. Instead of requiring the Northbridge to mediate all reset operations, the Southbridge directly provides CPU reset functionality through the CPU_RST# signal. This intermediary role reduces the complexity burden on the Northbridge and enables simpler, more targeted reset operations.
3Reliability
If the Northbridge delivers CPU reset signal to reset the processor, then the processor is reset, but the Northbridge must be reset first causing data loss
Solution Approach 1:
The patent inverts the traditional reset signal flow by having the Southbridge (rather than the Northbridge) generate and control the CPU reset signal. Instead of the Northbridge delivering the CPU reset signal after being reset itself, the Southbridge independently generates the CPU_RST# signal and delivers it directly to the processor. This inversion eliminates the dependency chain that causes Northbridge data loss, as the Southbridge does not require resetting to provide CPU reset functionality.
Data Source
AI summary
A computer reset method activated by a South Bridge to directly reset a Central Processing Unit (CPU). First, a trigger signal is received. A CPU reset signal is delivered by the South Bridge when receiving the trigger signal. Thereafter, the CPU is reset when receiving the CPU reset signal from the South Bridge via a North Bridge.