Tile-Based Rendering Cache with Delayed-Edge Replacement

Solution Overview

Problem

Tile-based rendering (TBR) systems face inefficiencies in power consumption and memory usage due to the 'edge effect,' where texture data at the boundaries of tiles is not reused promptly, leading to cache inefficiency and increased texture bandwidth compared to object-based rendering (OBR).

Innovation Solution

A cache memory system with dual associative cache units and delayed-replacement information to selectively store and retrieve cache lines based on access frequency and edge data relevance, allowing for efficient management of cache lines and reducing unnecessary data retrieval from external memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If tile-based rendering is used to reduce memory access frequency, then power consumption and memory consumption are reduced, but cache efficiency deteriorates due to the edge effect where texture data at tile boundaries is not reused promptly

Engineering Contradiction:

Improvepower consumptionVSAvoidcache efficiency

Core Design Contradiction:

Loss of energyVSProductivity

Solution Approach 1:

The patent applies local quality by treating edge cache lines differently from internal cache lines. Edge cache lines (those containing texture data at tile boundaries) are identified and given special handling through delayed replacement, while internal cache lines follow standard replacement policies. This localized differentiation resolves the contradiction by preserving edge data longer to capture potential reuse across tile boundaries, thereby improving cache efficiency without significantly increasing power consumption.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent implements preliminary action by pre-identifying and flagging edge cache lines before replacement decisions are made. The delayed-replacement information is prepared in advance for each cache line, allowing the system to quickly determine which lines should be protected from replacement. This advance preparation enables efficient cache management that improves cache efficiency while maintaining the low-power benefits of tile-based rendering.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If texture data at tile boundaries is stored in cache for longer periods, then cache efficiency is improved, but cache memory usage increases

Engineering Contradiction:

Improvecache efficiencyVSAvoidcache memory usage

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The patent applies local quality by treating edge cache lines differently from internal cache lines. Edge cache lines (those containing texture data at tile boundaries) are identified and given special handling through delayed replacement, while internal cache lines follow standard replacement policies. This localized differentiation resolves the contradiction by preserving edge data longer to capture potential reuse across tile boundaries, thereby improving cache efficiency without significantly increasing power consumption.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent implements a delayed replacement strategy where edge cache lines are not immediately discarded when cache space is needed, but rather held longer to allow for potential reuse. The system recovers cache space by replacing non-edge lines first, and only after a delay does it replace edge lines if they haven't been reused. This approach improves cache efficiency by capturing boundary reuse patterns while managing cache memory usage through selective retention.

Inventive Principle:

Principle #34Discarding and recovering

3Device complexity

If a simple cache replacement policy is used, then device complexity is reduced, but cache performance deteriorates due to inability to handle edge effects

Engineering Contradiction:

Improvecache replacement mechanismVSAvoidcache performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent applies segmentation by dividing cache lines into two categories: edge cache lines and internal cache lines. This segmentation is achieved through simple classification based on the cache line's position relative to tile boundaries. The system then applies different replacement policies to each segment, with edge lines receiving delayed replacement treatment. This segmentation approach improves cache performance by addressing edge effects while keeping the overall mechanism relatively simple.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary action by pre-identifying and flagging edge cache lines before replacement decisions are made. The delayed-replacement information is prepared in advance for each cache line, allowing the system to quickly determine which lines should be protected from replacement. This advance preparation enables efficient cache management that improves cache performance while maintaining relatively simple device complexity.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS9176880B2Cache memory system for tile based rendering and caching method thereof

Publication Date: 2015.11.03 SAMSUNG ELECTRONICS CO LTD

AI summary

A cache memory system and a caching method for a tile-based rendering may be provided. Each of cache lines in the cache memory system may include delayed-replacement information. The delayed-replacement information may indicate whether texture data referred to at a position of an edge of a tile is included in a cache line. When a cache line corresponding to an access-requested address is absent in the cache memory system, the cache memory system may select and remove a cache line to be removed from an associative cache unit, based on delayed-replacement information.