Adaptive LDO Biasing for Low-Error Digital-to-Time Converters

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Solution Overview

Problem

Radio frequency (RF) devices with digital polar transmitter (DPTX) circuits face issues with power supply rejection due to variable current consumption, leading to errors in phase modulation caused by changes in supply voltage and settling time.

Innovation Solution

A low dropout regulator (LDO) circuit with adjustable bias current and a fast control loop is implemented to regulate the power supply, reducing the settling time and minimizing the impact of power supply disturbances on phase modulation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If a regulated power supply is used to handle variable current consumption, then power supply stability is improved, but power supply rejection remains poor due to slow settling time

Engineering Contradiction:

Improvepower supply stabilityVSAvoidpower supply rejection

Core Design Contradiction:

Stability of the object's compositionVSReliability

Solution Approach 1:

The patent implements a dynamic bias current adjustment mechanism that adapts the LDO regulator's bias current based on the instantaneous current consumption of the DPTX circuit. This dynamic adaptation allows the regulator to respond quickly to current transients while maintaining stability, resolving the contradiction between stability and rejection performance.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent employs a feedback mechanism where the bias current of the LDO regulator is adjusted according to the current consumption state of the DPTX circuit. This feedback loop enables the power supply to anticipate and compensate for current transients, improving power supply rejection while maintaining stability.

Inventive Principle:

Principle #23Feedback

2Speed

If bias current is increased to reduce settling time, then response speed is improved, but power consumption increases

Engineering Contradiction:

Improvesettling timeVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent dynamically adjusts the bias current based on the operational state of the DPTX circuit. During transient conditions requiring fast response, the bias current is increased to reduce settling time. During steady-state operation, the bias current is reduced to minimize power consumption, thus resolving the contradiction between speed and energy usage.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the bias current parameter adaptively based on the current consumption state. By varying this parameter from high during transients to low during steady-state, the system achieves fast settling when needed while minimizing power consumption during normal operation.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentEP3264706B1Low drop out compensation technique for reduced dynamic errors in digital-to-time converters

Publication Date: 2023.07.05 INTEL IP CORP

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AI summary

An apparatus comprises a radio frequency (RF) transceiver circuit; a phase modulator that comprises digital-to-time converter (DTC) circuitry configured to convert a digital value to a specified signal phase of a signal transmitted by the RF transceiver circuit; low drop out regulator (LDO) circuitry operatively coupled to the DTC circuitry, wherein a bias current of the LDO circuitry is adjustable; and logic circuitry operatively coupled to the LDO circuitry and DTC circuitry, wherein the logic circuitry is configured to set the adjustable bias current of the LDO circuitry according to a digital value input to the DTC circuitry.