Deep Learning Accelerator Path Switching for Adaptive Memory Bandwidth
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Solution Overview
Problem
Existing deep learning accelerators operate under predetermined worst-case scenarios, leading to overdesign and inability to adaptively adjust to current system workload levels, thus inefficiently utilizing resources.
Innovation Solution
A deep learning accelerator with a controller circuit that generates control signals based on traffic data to dynamically select between high and low access bandwidth paths for memory access, adjusting computational paths according to system workload, thereby optimizing resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the deep learning accelerator is designed and configured during the design phase with considering the possible highest workload level (worst-case scenario), then the system performance under high workload is ensured, but the accelerator becomes overdesigned and cannot adaptively adjust to current system workload level
Solution Approach 1:
The patent implements dynamic adaptability by providing multiple computational paths (first path with high access bandwidth, second path with low access bandwidth) and dynamically selecting between them based on current system workload level. The controller circuit determines the current workload level and generates control signals to switch between computational paths, enabling the accelerator to adapt its resource allocation to actual demand rather than being fixed at worst-case design parameters.
2Reliability
If the deep learning accelerator is designed for highest workload level, then performance under worst-case scenario is guaranteed, but resource utilization efficiency deteriorates under lower workload levels
Solution Approach 1:
The patent changes operational parameters by providing multiple computational paths with different access bandwidth characteristics. When workload is high, the system uses the first computational path with high access bandwidth to maintain performance. When workload is low, it switches to the second computational path with low access bandwidth, thereby matching resource consumption to actual demand and improving energy efficiency.
3Ease of manufacture
If the accelerator operates under predetermined operating conditions without considering current system workload level, then design and configuration is simplified, but the accelerator lacks capability to adaptively adjust to varying workload levels
Solution Approach 1:
The patent implements multi-functionality by designing the accelerator to support multiple computational paths that can handle different workload scenarios. The controller circuit universally manages both high-workload and low-workload operations by selecting appropriate computational paths, making the system capable of handling a wide range of workload conditions rather than being optimized for a single predetermined operating condition.
Data Source
AI summary
A deep learning accelerator includes a controller circuit, a processing elements (PE) array circuit, and a memory access circuit. The controller circuit generates a control signal according to traffic data. The PE array circuit operates a neural network model. A layer computation of the neural network model includes first and second paths, and the PE array circuit selects a path from the first and second paths according to the control signal to execute the layer computation via the selected path. The PE array circuit accesses a memory circuit via the memory access circuit to execute the layer computation. When the layer computation is executed via the first path, the PE array circuit accesses the memory circuit with first bandwidth. When the layer computation is executed via the second path, the PE array circuit accesses the memory circuit with second bandwidth. The first bandwidth is higher than the second bandwidth.