Adaptive Memory Cell Programming for Read Performance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory systems face challenges in optimizing data storage and retrieval performance due to issues like bit error rates and the need for adaptive error recovery, which can lead to increased operation delays and bit error rates when storing multiple bits per memory cell.
Innovation Solution
A memory sub-system that adaptively selects programming modes for memory cells based on usage parameters and error recovery options to optimize storage capacity and performance, using predictive models to determine the best mode for storing data and employing techniques like error correction codes to manage bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bits per memory cell are stored to increase storage capacity, then storage capacity is improved, but bit error rate increases
Solution Approach 1:
The system dynamically changes programming parameters such as voltage levels, pulse widths, and programming modes (e.g., SLC vs. MLC modes) based on real-time error rates and usage patterns. When error rates increase, the system adjusts parameters to be more conservative, reducing the number of bits stored per cell to maintain reliability while optimizing storage capacity under varying conditions
Solution Approach 2:
The memory system transitions from static to dynamic programming modes, allowing cells to be programmed in different modes (SLC, MLC, TLC) depending on current workload requirements and error conditions. This dynamic adaptation enables the system to optimize between storage capacity and reliability in real-time based on actual operating conditions
2Reliability
If adaptive error recovery techniques are implemented to reduce bit error rates, then reliability is improved, but operation delay increases
Solution Approach 1:
The system performs preliminary error checking and recovery operations during the programming phase rather than waiting for read operations. By proactively detecting and correcting errors before they affect data retrieval, the system reduces the need for time-consuming read retries and minimizes operation delays during actual data access
Solution Approach 2:
The system implements continuous feedback loops that monitor error rates during programming and reading operations, dynamically adjusting error recovery intensity and programming parameters. When error rates are low, the system reduces error recovery overhead to minimize delays; when error rates increase, it intensifies error recovery operations to maintain reliability
3Reliability
If conservative programming modes are used to reduce bit error rates, then reliability is improved, but storage capacity decreases
Solution Approach 1:
The memory system dynamically switches between conservative (SLC) and aggressive (TLC/QLC) programming modes based on real-time conditions including error rates, workload requirements, and cell wear levels. This enables the system to use conservative modes only when necessary for reliability while maximizing storage capacity during normal operation
Solution Approach 2:
The system changes programming parameters such as voltage thresholds, programming pulses, and verification criteria based on current operational context. By adjusting these parameters dynamically, the system can achieve higher storage capacity when conditions permit while maintaining reliability through more conservative parameters when error rates increase
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves data retrieval performance by reducing read retry and bit error rates, while dynamically adjusting storage capacity to balance operation delay and error recovery capabilities.
Implementation Method 1
A memory cell can store one or more bits of data. In general, a memory cell stores data by applying a voltage or a pattern of voltage to the memory cell during a program/write operation. The program/write operation sets the memory cell in a state that corresponds to the data being programmed/stored into the memory cell.
Implementation Method 2
The read operation determines the state of the memory cell by applying a voltage and determining whether the memory cell becomes conductive at a voltage corresponding to a pre-defined state.
Data Source
AI summary
Systems, methods and apparatus to determine, in response to a command to write data into a set of memory cells, a programming mode of a set of memory cell to optimize performance in retrieving the data back from the set of memory cells. For example, based on usages of a memory region containing the memory cell set, a predictive model can be used to identify a combination of an amount of redundant information to be stored into the memory cells in the set and a programming mode of the memory cells to store the redundant information. Increasing the amount of redundant information can increase error recovery capability but increase bit error rate and/or increase time to read. The predictive model is trained to predict the combination to optimize read performance.