Read-Only Memories TRIZ Cases

A control circuit adjusts bit line charging voltage during pre-charge to determine threshold voltage.

Controller selects optimal demarcation voltage based on elapsed write time to reduce read latency and mitigate threshold drift.

Predictive models adjust voltage and redundancy levels to reduce bit error rates and read retries.

A semiconductor memory device adjusts start program voltage using flag cell data to optimize threshold levels.

A memory circuit uses programmable signal lines and shared transistors to encode multiple bits of information.

A write circuit applies programming pulses to phase change memory elements and adjusts parameters based on sensed resistance.

Detects broken word lines by comparing programmed threshold voltages against reference levels to identify under-programmed storage elements.

A noise reduction component manages quiet and high noise events by assigning priorities to independent plane driver circuits.

Dynamic voltage elevation enables rapid data transfer from volatile to non-volatile memory, resolving battery charge time limitations.

A peripheral voltage control circuit provides dynamic bit line precharge voltages to enhance semiconductor memory area efficiency.

Segmented memory arrays switch bitcell types to reduce leakage by 50% and read-dynamic power by 30% without area penalty.

Separating pre-charge select scans from voltage transitions eliminates current spikes during memory programming operations.

A ferroelectric NAND memory device applies differentiated voltage levels to selected and unselected word lines during programming operations.

A row decoding circuit with a dummy unit and shared drive voltage reduces area while maintaining speed.

Adaptive programming adjusts voltage and pulse width based on individual cell performance to resolve speed versus accuracy tradeoffs.

A charge pump output floating scheme manages power in non-volatile memory systems by regulating high voltage generation.

Storing data in idle sub-memory devices reduces controller load and enhances performance by minimizing buffer memory access.

Local feedback in a sense amplifier adjusts bit line voltage based on cell current, reducing settling time and variability across scaled memory devices.

Shared decoding circuits and integrated voltage boosting blocks reduce the area occupied by the row selector while enabling efficient programming operations.

Control logic increments verify voltages during program loops, resolving reliability issues caused by static verification methods.

Classifying memory sub blocks into groups enables dynamic parameter selection, resolving the trade-off between erase performance and management complexity.

A detection circuit measures bit line pre-charge time to dynamically adjust verify stage timing parameters in non-volatile memory operations.

Preliminary threshold voltage checks on select transistors reduce bad block processing time while maintaining detection accuracy.

Dynamically adjusts erase-verify sensing thresholds based on partial programming state to resolve contradictions between erase speed and reliability.

A variable reference voltage circuit decouples write voltages for programming, erasing, and reading operations in non-volatile memory arrays.

An embedded AI circuit adjusts input signals to ideal levels based on detected environmental data and performance metrics.

A NAND flash memory read circuit applies positive voltage to the source line during operation.

Series native MOS transistors isolate high-voltage impacts on storage devices, reducing leakage currents and power consumption in OTP memory arrays.

Edge sense amplifiers detect data from memory cell arrays using reference signals generated by dedicated edge arrays.

A sense amplifier circuit detects cell current differences between information and reference cells in a memory array.

Adjusting local read pass voltages based on cell proximity reduces back pattern noise and threshold shifts in sub-56nm NAND flash.

Column redundancy techniques shift data between memory columns and redundancy columns using IO multiplexing logic.

A programming method adjusts threshold voltages of flash memory cells to secure read margins between data states.

Pre-charging unselected memory groups reduces program disturb during non-volatile storage element programming.

A monitor module increments counters for read recovery operations to proactively remove defective erasure blocks, improving garbage collection accuracy.

Multiple writes accumulate excess charge on floating gate transistors, maintaining data integrity against ionizing radiation damage.

Grouping global wordline drivers around shared bias components reduces periphery area consumption while supporting more wordlines.

Estimates probability density functions from decoded codewords to determine the optimal center read reference voltage for non-volatile memory pages.

A NAND flash column decoder divides the data bus into two portions connected by a switch to reduce peak current.

One-time programmable memory blocks divide into two sections to store status and data, eliminating external record units that increase device complexity.

Dynamic stage switching in a universal charge pump circuit reduces chip area and power consumption while maintaining stable voltage levels.

A semiconductor device uses a latch circuit to store test results for direct non-volatile memory programming.

Position-dependent voltage lowering on select lines prevents hot electron disturbance caused by large electric fields between word lines.

A shunt device at the column decoder output directs a CLEAN pulse to remove spurious charges from floating nodes.

Counting failed adjacent bit lines triggers double programming pulses or increased Vpass voltage to reduce program disturb and read errors.

Segmenting memory and selection transistors resolves the trade-off between data retention reliability and operating speed.

Distinct pass voltages on grouped unselected word lines suppress program and pass disturb shifts in 3D NAND memory cells.