Memory Device Programming Compensation for Program Disturb
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Solution Overview
Problem
Flash memory devices suffer from program disturb, where unprogrammed memory cells experience threshold voltage changes due to voltage applications and coupling effects from adjacent cells, leading to read errors, and existing methods to mitigate this issue, such as using fixed pairs of programming pulses, result in increased programming time and other drawbacks.
Innovation Solution
The method involves counting potential CS2 situations, where adjacent bit lines have failed program verify operations, and if the count exceeds a threshold, compensation is applied by generating double programming pulses or increasing the Vpass voltage on unselected word lines, ensuring that memory cells on either side of an inhibited bit line are not programmed simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed number of pairs of programming pulses is used to reduce program disturb, then read errors are reduced, but programming time increases
Solution Approach 1:
The patent applies dynamics by transitioning from a fixed number of programming pulse pairs to a variable number of pairs based on real-time detection of CS2 situations. The system dynamically adjusts the programming pulse sequence according to the actual number of inhibited bit lines encountered during programming, allowing the process to adapt between minimum (no CS2 situations) and maximum (all bit lines inhibited) scenarios, thereby reducing unnecessary programming time while maintaining reliability.
Solution Approach 2:
The patent implements feedback by introducing detection circuitry that monitors programming operations to identify CS2 situations (inhibited bit lines with adjacent programmed cells). This feedback mechanism enables the control logic to adjust the programming pulse sequence in real-time, generating additional pulse pairs only when CS2 situations are detected, thus avoiding wasted time on unnecessary programming operations while ensuring read error prevention when needed.
2Productivity
If adjacent bit lines are programmed simultaneously to improve productivity, then programming speed increases, but program disturb increases
Solution Approach 1:
The patent applies segmentation by dividing the programming operation into distinct phases based on bit line inhibition status. When CS2 situations are detected (inhibited bit lines with adjacent programmed cells), the system segments the programming process into separate pulse pairs for different bit line groups, preventing simultaneous programming of adjacent inhibited bit lines and thereby reducing program disturb while maintaining overall productivity through efficient sequencing.
Solution Approach 2:
The patent implements preliminary action by detecting CS2 situations before executing programming operations. The detection circuitry identifies inhibited bit lines and their adjacent programmed cells in advance, allowing the control logic to pre-plan the programming pulse sequence to avoid simultaneous programming of adjacent inhibited bit lines, thus preventing program disturb before it occurs while maintaining programming speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces program disturb by compensating for the number of failed adjacent bit lines, thereby minimizing threshold voltage changes and read errors, while maintaining efficient programming operations.
Implementation Method 1
Each of the cells within a block can be electrically programmed, such as by charging the charge storage structure. The data in a cell of this type is determined by the presence or absence of the charge in the charge storage structure.
Implementation Method 2
Changes in threshold voltage of the memory cells, through programming of charge storage structures (e.g., floating gates or charge traps)
Implementation Method 3
the adjacent series strings of memory cells, on either side of the inhibited series string, can affect the threshold voltages of the inhibited memory cells by floating gate-to-floating gate capacitive coupling between memory cells
Data Source
AI summary
Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells. A number of potential CS2 situations are detected. If the number of detected potential CS2 situations is greater than a threshold, programming compensation for a CS2 situation is used in a subsequent programming operation.