Latch Scan Timing Optimization for Memory Current Spikes
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Solution Overview
Problem
Current memory devices experience current spikes during program operations due to overlapping scan operations and voltage increases, which can lead to inefficiencies and potential errors in data state verification.
Innovation Solution
Optimizing the timing of latch scan operations by performing the PCHSEL scan earlier and the FF fill operation later, or delaying the increase of unselected word line voltages to avoid overlaps and reduce current peaks, thereby minimizing the risk of undesirable current spikes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If latch scan operations and voltage increases are performed concurrently during program operations, then operational efficiency is maintained, but current spikes occur leading to potential errors and inefficiencies
Solution Approach 1:
The patent applies preliminary action by performing the PCHSEL scan operation before increasing the voltages of unselected word lines, rather than concurrently. This timing separation ensures that the latch scan completes its read operations before the voltage increase begins, eliminating the current spike that occurs when both operations overlap. The scan operation is initiated in advance of the voltage transition, allowing clean separation of the two operations in time.
2Object-affected harmful factors
If the timing of latch scan operations is delayed to allow voltage increases to complete, then current spikes are reduced, but scan operation time increases
Solution Approach 1:
The patent resolves this contradiction by performing the latch scan operation in advance, before the voltage increase begins. This preliminary timing arrangement allows the scan to complete its critical read operations during a low-current period, avoiding the need to wait for voltage transitions to complete. The total time is optimized by overlapping the scan preparation with earlier program loop phases rather than delaying after voltage increases.
3Object-affected harmful factors
If PCHSEL scan and FF fill operation timing are optimized separately, then current spike reduction is achieved, but operational complexity increases
Solution Approach 1:
The patent merges the timing optimization of PCHSEL scan and FF fill operations into a unified approach. Both operations are scheduled to complete before the voltage increase of unselected word lines begins. The control circuitry manages both operations together as a coordinated sequence, reducing the need for separate complex timing mechanisms. The scan and fill operations are integrated into the same timing window before the voltage transition.
Data Source
AI summary
Apparatuses and techniques are described for avoiding current consumption peaks during a program operation for a memory device. The timing of scan operations of latches is adjusted to avoid overlapping with an increase in word line voltages. The scan operations can include a pre-charge select scan, which identifies memory cells subject to a verify test, and a fill operation for latches of memory cells which fail a verify test in a prior program loop. The pre-charge select scan can occur before the increase in the word line voltages, while the fill operation occurs after the increase in word line voltages. In another approach, the start of the increase in the word line voltages is delayed when a state bit scan is expected to take a relatively long time, e.g., when a verify test is passed in a prior program loop.