Row Selector Area Reduction in Semiconductor Memory Devices
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Solution Overview
Problem
The existing semiconductor memory devices, particularly flash memories, face challenges in optimizing the area-to-data storage ratio due to the large area occupied by the row selector, especially as the number of sectors increases, which is exacerbated by the need for high voltages during programming and erasing operations.
Innovation Solution
The proposed solution involves a memory device with a modified structure that includes a plurality of memory cells grouped into sectors, shared decoding and selecting circuits, and voltage boosting blocks to generate shifted signals, reducing the overall size by minimizing the area occupied by level shifters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of sectors in the memory is increased, then the data storage capability is improved, but the area occupied by the row selector increases
Solution Approach 1:
The patent divides the row selector into two separate decoding circuits: a first decoding circuit that generates common decoding signals shared by all sectors, and a second decoding circuit for each sector that generates sector-specific selection signals. This segmentation allows the common decoding functionality to be shared across sectors, reducing the overall area of the row selector while maintaining support for multiple sectors.
Solution Approach 2:
The first decoding circuit is designed to be universal and shared by all memory sectors, generating decoding signals that are common to every sector. This multi-functional approach eliminates the need for separate decoding circuits in each sector, thereby reducing the total area occupied by the row selector while supporting an increased number of sectors.
2Adaptability or versatility
If level shifters are added to the row selector for voltage shifting, then programming and erasing operations become enabled, but the area occupied by the row selector increases
Solution Approach 1:
The patent combines the voltage boosting functionality with the decoding circuits by integrating voltage boosting blocks within the first and second decoding circuits. This merging eliminates the need for separate level shifter components, achieving the required voltage shifting capability while minimizing the additional area that would be occupied by standalone level shifters.
Solution Approach 2:
The voltage boosting blocks act as intermediary components that generate the necessary high voltages (such as -9V for erasing and 12V for programming) from the supply voltage. These intermediary voltage boosting circuits are integrated into the decoding structure, providing the required voltage adaptation without requiring separate level shifting stages that would increase area.
Data Source
AI summary
A memory device having a plurality of memory cells grouped in at least two memory sectors is disclosed. A first decoding circuit operable to receive address codes of the plurality of memory cells and to generate a plurality of decoding and selecting signals in response to the address codes. A plurality of second decoding circuits are coupled to the first decoding circuit and operable to generate driving signals for the memory cell address signal lines based at least in part on the plurality of decoding and selecting signals. A voltage shifting circuit is operable to generate a shift in the voltage of the plurality of decoding and selecting signals for generating a plurality of shifted voltage decoding and selecting signals and to provide the shifted decoding and selecting signals to the plurality of second decoding signals for generating the drive signals.