Memory Circuit Layout Structure for Multi-Bit Encoding
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Solution Overview
Problem
Conventional ROM cells and memory architectures face inefficiencies in area usage, high cost, and high power consumption, necessitating improved designs for on-chip read-only memory.
Innovation Solution
A memory circuit design featuring transistors with programmable signal lines and multiple information lines, where the connection of information lines to the transistors is dynamically controlled to encode and store multiple bits of information, optimizing layout and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional ROM cell structures are used, then memory functionality is achieved, but area efficiency is poor and cost is high
Solution Approach 1:
The patent merges multiple bits of information into a single memory cell by utilizing different voltage levels on a shared signal line. Instead of requiring separate storage elements for each bit, the invention combines multiple information bits by encoding them in the voltage state of a common line, thereby reducing the number of transistors and contacts needed per bit of stored information.
Solution Approach 2:
The signal line serves multiple functions: it acts as both a data line and a programmable voltage source for encoding information. The same signal line is used to represent multiple bits of information through different voltage levels, making the memory cell structure more versatile and reducing the need for additional dedicated lines or components.
2Use of energy by stationary object
If conventional ROM cell structures are used, then memory functionality is achieved, but power consumption is high
Solution Approach 1:
By merging multiple information bits into a single memory cell through voltage-level encoding on a shared signal line, the invention reduces the total number of active components (transistors and contacts) that would otherwise be required. Fewer components mean lower static and dynamic power consumption while maintaining or increasing memory density.
3Productivity
If multi-bit information coding is implemented, then memory density increases, but device complexity increases
Solution Approach 1:
The invention uses parameter changes (voltage levels) on the signal line to encode multiple bits of information. Instead of adding more physical storage elements, the system varies the voltage parameter to represent different data states, thereby increasing memory density without proportionally increasing circuit complexity.
Data Source
AI summary
A memory circuit includes a transistor, a signal line and a plurality of information lines. The transistor includes a first electrode, a second electrode and a control electrode. The transistor is included in a memory cell. The signal line is connected to the first electrode of the transistor. The voltage on the signal line is programmable. At most one of the information lines is connected to the second electrode of the transistor via a contact. Information stored in the memory cell is coded according to the voltage programmed on the signal line and an option of which information line the contact should connect to the second electrode of the transistor.