Noise Reduction in Multi-Plane Memory via Priority Scheduling
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Solution Overview
Problem
In multi-plane memory devices, concurrent memory access operations generate noise on shared common supply lines, leading to ground bounce and sensing errors, particularly as the number of independent plane driver circuits increases, impacting the performance and reliability of memory access operations.
Innovation Solution
A noise reduction component manages quiet and high noise events by assigning priorities to independent plane driver circuits based on the order of received commands, suspending conflicting operations to minimize noise on shared supply lines, thereby preventing ground bounce and improving memory access accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If concurrent memory access operations are performed on multiple planes, then productivity is improved, but noise on shared supply lines increases causing ground bounce and sensing errors
Solution Approach 1:
The noise reduction component identifies quiet events in advance before they occur and schedules them to happen during time periods when no high noise events are predicted to occur, preventing noise interference before it can affect sensing operations
Solution Approach 2:
The system monitors the occurrence of quiet events and high noise events in real-time, using this feedback information to dynamically adjust the scheduling of memory access operations across different planes, ensuring that quiet events are not interrupted by subsequent high noise events
2Productivity
If the number of independent plane driver circuits is increased, then productivity is improved, but noise generation increases leading to ground bounce
Solution Approach 1:
The memory device is divided into multiple independent planes, each with its own driver circuit, allowing parallel access operations. The noise reduction component segments the management of these planes by independently tracking and scheduling quiet events and high noise events for each plane, preventing cumulative noise from causing ground bounce
Solution Approach 2:
The system dynamically adjusts the operation timing of different plane driver circuits based on real-time noise conditions. By making operations on certain planes dynamic and conditionally executable (based on noise event status), the system allows multiple driver circuits to operate in parallel without generating excessive cumulative noise
3Reliability
If memory access operations are suspended to reduce noise, then reliability is improved, but latency increases
Solution Approach 1:
By identifying and scheduling quiet events in advance during low-noise time periods, the system ensures reliable sensing operations without needing to suspend subsequent operations, thereby avoiding latency penalties while maintaining sensing accuracy
Solution Approach 2:
High noise events that are not critical are allowed to skip or be delayed only when a quiet event is currently executing, rather than suspending the quiet event. This rushing through of non-critical operations minimizes latency while still protecting critical sensing operations
Data Source
AI summary
A memory device includes a memory array comprising a plurality of planes and a plurality of independent plane driver circuits. The memory device further includes control logic to detect an occurrence of a high noise event associated with a first independent plane driver circuit of the plurality of independent plane driver circuits. The control logic is further to determine whether a quiet event associated with a second independent plane driver circuit of the plurality of independent plane driver circuits is concurrently occurring. Responsive to determining that the quiet event associated with the second independent plane driver circuit is concurrently occurring, the control logic is to manage execution of the high noise event and the quiet event based on respective priorities of the first and second independent plane driver circuits.