OTP Memory Array Isolation Modules Reduce Leakage
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Solution Overview
Problem
Conventional OTP memory technologies face issues with high power consumption, reliability, and complex voltage management due to lack of effective isolation and high-voltage impact on MOS transistors, leading to increased leakage currents and complex decoder designs.
Innovation Solution
The proposed OTP memory array incorporates a series of Native MOS transistors as isolation modules between storage and detection MOS transistors, utilizing multiple stages of high-voltage isolation devices to reduce crosstalk and voltage impact, allowing for low-voltage word and bit line selection, and eliminating the need for boost circuits and large decoder structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If no high-voltage isolation device is used, then device complexity is reduced, but reliability of MOS transistors under high-voltage impact deteriorates and leakage currents increase
Solution Approach 1:
The patent introduces a high-voltage isolation device (first isolation device) as an intermediary component between the bit line and the storage MOS transistor. This isolation device acts as a mediator that protects the storage MOS transistor from direct high-voltage impact while allowing the memory cell to function. The isolation device transfers and isolates the high-voltage signal, preventing harmful effects on the storage transistor.
2Device complexity
If no read isolation device is used, then device complexity is reduced, but power consumption increases due to global clearing requirements
Solution Approach 1:
The patent divides the memory array into independently controllable units by introducing a second isolation device (read isolation device) that enables selective row-by-row clearing. This segmentation allows the system to clear only the necessary memory rows rather than performing global clearing operations, significantly reducing power consumption during read operations.
3Manufacturing precision
If thick gate oxygen devices are used in medium-high voltage paths, then manufacturing precision is improved, but Vt voltage drop loss increases and read voltage becomes high
Solution Approach 1:
The patent applies different device characteristics to different parts of the circuit based on voltage requirements. Native MOS transistors with zero threshold voltage are used specifically in high-voltage paths (bit line to storage transistor) where voltage drop would be problematic, while conventional MOS transistors can be used in low-voltage paths. This localized optimization of device properties minimizes overall voltage drop and power loss.
Data Source
AI summary
A one time programmable OTP memory array and a read and write method thereof are provided. The OTP memory array includes M×N OTP memories, the OTP memories each include a storage MOS transistor, a first MOS transistor, a second MOS transistor and a detection MOS transistor, an isolation module is disposed between a control terminal of the detection MOS transistor and the storage MOS transistor; the isolation module includes at least one isolation MOS transistor; and in the array, a gate of each storage MOS transistor is connected to a same storage control point, each isolation MOS transistor is distinguished based on a distance from the storage MOS transistor, and gates of isolation MOS transistors with a same distance from the storage MOS transistor are connected to a same isolation control point.