Non-Volatile Memory Timing Adjustment via Bit Line Pre-Charge Detection
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Solution Overview
Problem
The variability in manufacturing process and operating conditions, such as temperature and data patterns, affects the consistency of read and program operation times in high-density memory devices, leading to potential errors and significant delays in memory operations.
Innovation Solution
A self-adaptive timing adjustment system that measures the speed of bit lines or word lines during initial stages of operations and applies adjustments to later stages, using detection circuits to determine pre-charge times and setting corresponding verify times or settling periods to optimize programming and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If detection circuits are used to detect read or programming errors and adjust timing parameters, then reliability is improved, but loss of time increases due to significant delay in execution
Solution Approach 1:
The patent applies preliminary action by measuring bit line pre-charge time before the actual read or program operation. The detection circuit measures the time for the bit line to charge from a reference voltage to a threshold voltage during an initial stage, and this measurement is used to predetermined settling times for later verify stages. This preliminary measurement enables timing adjustment without delaying the main operation execution.
Solution Approach 2:
The patent implements feedback by using the measured bit line pre-charge time to dynamically adjust settling times for subsequent verify stages. The detection circuit provides feedback about the actual charging speed of bit lines, which is then used to optimize the timing parameters for error detection. This feedback mechanism allows the system to adapt to process variations while maintaining efficient operation timing.
2Quantity of substance
If higher density memory devices are fabricated, then storage density is improved, but manufacturing precision deteriorates due to process variations affecting operation times
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting timing parameters based on measured bit line charging characteristics. Instead of using fixed timing values, the system measures the actual pre-charge time and uses this to determine appropriate settling times for verify stages. This allows the memory device to compensate for manufacturing process variations and maintain consistent operation timing across different process conditions.
Solution Approach 2:
The patent implements dynamics by transitioning from static, predetermined timing values to dynamic, measured timing values. The detection circuit continuously measures bit line charging speed, and the system adapts its timing parameters in real-time based on these measurements. This dynamic approach enables the high-density memory device to maintain manufacturing precision despite process variations by adjusting timing to match actual physical conditions.
3Reliability
If timing parameters are adjusted to account for temperature and data pattern variations, then reliability is improved, but device complexity increases due to additional detection and adjustment circuits
Solution Approach 1:
The patent applies universality by designing the detection circuit to perform multiple functions: it measures bit line pre-charge time, determines settling times for verify stages, and provides timing adjustment for both read and program operations. The same detection and measurement infrastructure is used across different operation types and temperature conditions, reducing the need for separate specialized circuits for each function.
Solution Approach 2:
The patent implements self-service by enabling the memory device to automatically measure and adjust its own timing parameters without external intervention. The detection circuit is integrated within the memory device and autonomously measures bit line charging characteristics, determines appropriate settling times, and applies these adjustments to subsequent operations. This self-adjusting capability reduces the need for external control circuitry and simplifies the overall system architecture.
Data Source
AI summary
A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programming operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.