NAND Flash Column Decoder Data Bus Segmentation
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Solution Overview
Problem
The increasing miniaturization of memory cells in NAND-type flash memory devices leads to a larger circuit area for peripheral circuits, resulting in slower data read/write processes due to increased data bus length and peak current requirements.
Innovation Solution
A nonvolatile semiconductor memory device with a column decoder that divides the data bus into two portions connected by a switch, allowing for separate precharging and operation of each portion, reducing the load on the data bus and peak current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are miniaturized to increase storage capacity, then the number of memory cells increases, but the circuit area of peripheral circuits increases and data bus length increases
Solution Approach 1:
The data bus is divided into multiple segments (first data bus portion and second data bus portion) that can be independently controlled. The switch selectively connects or disconnects these segments, allowing the data bus to be divided into smaller operational units. This segmentation reduces the effective length of the data bus during operations, thereby decreasing charging/discharging time and peak current requirements while supporting miniaturized memory cell arrays with higher storage capacity.
2Ease of operation
If data bus length increases due to larger peripheral circuit area, then data transceiving capability is maintained, but charging/discharging time increases
Solution Approach 1:
The data bus is segmented into multiple portions that can be independently activated. During data transceiving operations, only the necessary portion of the data bus is connected and activated, reducing the total capacitance that needs to be charged or discharged. This segmentation maintains full data transceiving capability while significantly reducing charging/discharging time by limiting the active bus length to only what is currently needed.
Solution Approach 2:
The switch dynamically connects or disconnects the first and second data bus portions based on operational requirements. This dynamic reconfiguration allows the data bus structure to adapt to different operating conditions, enabling fast charging/discharging when only partial bus functionality is needed while maintaining the ability to use the full bus length when complete data transceiving capability is required.
3Quantity of substance
If data bus length increases to support more memory cells, then storage capacity is increased, but peak current requirement increases
Solution Approach 1:
The data bus is divided into separable portions controlled by a switch. During read or write operations, only the necessary data bus portion is connected, reducing the total capacitance load. This segmentation allows the memory device to support miniaturized cells with higher storage capacity while reducing peak current requirements, as the peak current is now proportional to the active bus portion rather than the total bus length.
4Productivity
If peripheral circuit area increases to handle more memory cells, then data processing capability is maintained, but data bus length and operation time increase
Solution Approach 1:
The data bus is segmented into controllable portions that can be independently managed. This segmentation allows the peripheral circuits to maintain full data processing capability by activating only the necessary bus portions during each operation. The reduced active bus length decreases the time required for data bus operations, thereby improving overall productivity despite the increased peripheral circuit area needed to support more memory cells.
Data Source
AI summary
A nonvolatile semiconductor memory device includes memory cells arranged into memory strings with word lines each connected to a different memory cell of the memory strings. The device also includes bit lines each connected to a different memory string and a column decoder connected to the bit lines. The column decoder includes sense amplifiers, data latches, and a data bus connecting sense amplifiers and data latches. The data bus is divided into at least two portions and includes a first portion connected to a second portion by a switch.