Column Redundancy Techniques for Memory Yield and Area Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional circuit designs face inefficiencies in memory access operations due to area-inefficient input-output (IO) redundancy at the transistor level, leading to reduced yield and performance in memory instances, particularly in system-on-a-chip (SoC) designs.
Innovation Solution
Implementing column redundancy techniques at the SoC level through IO multiplexing, which shifts data between memory columns and redundancy columns to enhance area efficiency and reduce instance-level overhead, thereby improving power, performance, and area (PPA) in memory applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If IO redundancy is implemented at transistor level, then memory yield is improved, but area efficiency deteriorates and PPA metrics degrade
Solution Approach 1:
The patent moves IO redundancy from transistor level (2D plane) to memory column level (adding dimension of memory organization), where redundancy columns are integrated into the memory array structure. This dimensional shift allows shared redundancy resources across multiple memory instances, improving area efficiency while maintaining yield benefits.
Solution Approach 2:
The patent creates universal IO redundancy columns that serve multiple memory instances simultaneously. The redundancy columns and associated multiplexing logic are designed to be shared resources that can handle errors across different memory blocks, rather than dedicating separate redundancy circuits to each instance. This multi-functionality reduces overall area overhead.
2Speed
If memory instances are made small to meet performance targets, then access speed is improved, but IO redundancy area efficiency deteriorates
Solution Approach 1:
The patent merges IO redundancy resources across multiple small memory instances by implementing shared redundancy columns at the memory array level. Instead of each small instance having its own dedicated redundancy circuits, the system combines redundancy resources that serve multiple instances, reducing total area while maintaining the performance benefits of small instance sizes.
3Device complexity
If modern IO multiplexing is used with transistor level redundancy, then circuit complexity is reduced, but area efficiency deteriorates and PPA metrics worsen
Solution Approach 1:
The patent introduces memory column-level multiplexing as an intermediary layer between the memory arrays and IO interfaces. This column-level multiplexing mechanism efficiently manages access to redundancy columns while sharing IO resources across multiple memory instances, achieving better area efficiency compared to transistor-level approaches while maintaining manageable circuit complexity.
Data Source
AI summary
Various implementations described herein are directed to a device having memory architecture with an array of memory cells arranged in multiple columns with redundancy including first columns of memory cells disposed in a first region along with second columns of memory cells and redundancy columns of memory cells disposed in a second region that is laterally opposite the first region. The device may have column shifting logic that is configured to receive data from the multiple columns, shift the data from the first columns in the first region to a first set of the redundancy columns in the second region, and shift data from the second columns in the second region to a second set of the redundancy columns in the second region.