Configurable Memory Bitcell Optimization via Segmentation
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Solution Overview
Problem
There is a need for improved power, performance, and area (PPA) optimization in integrated circuit devices, particularly in memory storage capacity and read/write capabilities, to meet the increasing demands of portable computing devices.
Innovation Solution
The method involves determining thresholds for read current, leakage current, or minimum assist voltage to identify a logic design and bitcell-type, allowing for dynamic optimization of memory compilers and bitcell-types to switch between high-speed and low-power modes without area penalty, using different bitcell-types with similar aspect ratios to optimize memory architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single bitcell-type is used in memory architecture, then device complexity is reduced, but power, performance, and area optimization capability deteriorates
Solution Approach 1:
The memory array is segmented into multiple regions, each containing different bitcell-types (e.g., first bitcell-type with higher leakage current for high-speed operation, second bitcell-type with lower leakage current for low-power operation). This segmentation allows independent optimization of different memory regions for different operational requirements without increasing overall device complexity.
Solution Approach 2:
The memory architecture dynamically selects and switches between different bitcell-types based on operational requirements. A control mechanism enables the system to activate specific bitcell-types in specific regions according to real-time power, performance, and area requirements, providing adaptability without permanent complexity.
2Speed
If high-speed bitcell-types are used throughout the memory array, then read/write speed is improved, but power leakage increases
Solution Approach 1:
Different regions of the memory array are assigned different bitcell-types with locally optimized properties. Regions requiring high-speed access use bitcell-types with higher leakage current, while regions where power consumption is critical use bitcell-types with lower leakage current. This local differentiation resolves the contradiction by applying the right characteristics to the right locations.
Solution Approach 2:
The system changes operational parameters (leakage current characteristics) by selecting different bitcell-types based on requirements. Instead of using a fixed bitcell-type throughout, the architecture varies the leakage current parameter across different regions and operational modes, enabling high-speed operation where needed while minimizing power leakage elsewhere.
3Loss of energy
If low-power bitcell-types are used throughout the memory array, then power leakage is reduced, but timing performance deteriorates
Solution Approach 1:
The memory array is divided into regions with different quality characteristics. Regions where low-power operation is prioritized use bitcell-types with lower leakage current, while regions where timing performance is critical use bitcell-types with better speed characteristics. This spatial differentiation of quality attributes resolves the contradiction between power leakage and timing performance.
4Adaptability or versatility
If different bitcell-types with different aspect ratios are used, then power and performance attributes are optimized, but area efficiency deteriorates
Solution Approach 1:
The patent employs bitcell-types with asymmetric aspect ratios (different width-to-height ratios) to optimize for different functions. By strategically placing asymmetric bitcell configurations in different regions, the system achieves power and performance optimization while maintaining overall area efficiency through careful layout design.
Solution Approach 2:
The memory architecture achieves equipotentiality in terms of area utilization by ensuring that different bitcell-types are distributed in a balanced manner across the memory array. This distribution strategy maintains uniform area efficiency metrics while still allowing different regions to exploit the unique power-performance characteristics of their assigned bitcell-types.
Data Source
AI summary
According to one implementation of the present disclosure, a method includes determining one or more of a read current threshold, a leakage current threshold or a minimum assist voltage threshold; identifying a logic design, wherein the logic design is based the on one or more of the read current threshold, the leakage current threshold, or the minimum assist voltage threshold; identifying a bitcell-type and a corresponding version of the bitcell-type, wherein each version of the bitcell-type is associated with performance and power attributes of a bitcell of a memory array; and determining a memory optimization mode based on the identified logic design and the identified version of the bitcell-type.