NAND Flash Memory Read Voltage Control for Back Pattern Noise
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Solution Overview
Problem
As NAND-type flash memory becomes more highly integrated, interference noise between floating gates increases, making it difficult to maintain accurate threshold voltage states and data storage, especially as the design rule size decreases below 56 nm, leading to significant back pattern noise and threshold voltage shifts.
Innovation Solution
A method for controlling a non-volatile semiconductor memory device with a NAND string, where specific read and write-verifying procedures are implemented by applying varying read pass voltages to unselected memory cells adjacent to the selected cell, adjusting voltages to cancel threshold increases and reduce interference effects, thereby minimizing back pattern noise and maintaining accurate data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If higher integration is implemented to increase storage capacity, then data storage capacity is improved, but interference noise between floating gates increases causing threshold voltage shifts
Solution Approach 1:
The patent applies different read pass voltages to different groups of unselected memory cells based on their proximity to the selected cell. Specifically, a first read pass voltage is applied to unselected cells in a first group, and a second read pass voltage (higher than the first) is applied to unselected cells in a second group. This local differentiation compensates for the varying interference noise levels experienced by cells at different positions, thereby maintaining data storage accuracy in highly integrated structures.
2Manufacturing precision
If design rule size is reduced below 56 nm to increase integration density, then storage density is improved, but back pattern noise and threshold voltage shifts become significant
Solution Approach 1:
The patent changes the voltage parameter applied to unselected memory cells during read operations. By applying a higher second read pass voltage to unselected cells in the second group compared to the first read pass voltage applied to unselected cells in the first group, the patent compensates for threshold voltage shifts caused by reduced design rule sizes below 56 nm, thereby maintaining data storage reliability.
3Adaptability or versatility
If adjacent unselected memory cells are written later than the selected memory cell, then write flexibility is improved, but threshold voltage distribution widens due to interference
Solution Approach 1:
The patent applies a higher read pass voltage to unselected memory cells that will be written later (second group) before they are actually written. This preliminary action counteracts the interference noise that will be generated when these cells are subsequently written, preventing threshold voltage distribution widening and maintaining manufacturing precision.
Data Source
AI summary
A non-volatile semiconductor memory device has a NAND string, in which multiple memory cells are connected in series. A read procedure is performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof. In the read procedure, a first read pass voltage is applied to unselected memory cells except an adjacent and unselected memory cell disposed adjacent to the selected memory cell, the adjacent and unselected memory cell being completed in data write later than the selected memory cell, and a second read pass voltage higher than the first read pass voltage is applied to the adjacent and unselected memory cell.