Row Decoding Circuit for Dual-Bit Flash Memory

The patent merges multiple row decoding units into a single shared row decoding unit that serves multiple memory blocks. This is achieved by having one row decoding unit generate control signals that are distributed to multiple memory blocks, thereby reducing the total circuit area while maintaining proper decoding functionality for the entire memory array.

The row decoding unit is designed with multi-functionality to serve multiple memory blocks. A single row decoding unit can decode addresses for different memory blocks and generate appropriate control signals for various control-gate lines across multiple blocks, making the decoding circuit universal rather than dedicated to a single block.

The patent implements dynamic voltage adjustment in the driving transistors of the row decoding unit. The voltage supplied to these transistors is not fixed but is dynamically adjusted based on operational requirements. During critical operations requiring high speed, higher voltages are applied to maintain fast switching despite smaller transistor areas, while during less critical operations, lower voltages suffice, thus maintaining small area without permanently sacrificing speed.

The patent changes the voltage parameter dynamically to compensate for the reduced transistor area. By adjusting the voltage level supplied to the driving transistors, the patent optimizes the balance between transistor size and switching speed, allowing small transistors to achieve adequate driving speed through higher voltage operation when needed.

The patent segments each memory unit into two separate memory bits (first and second memory bits) with separate control-gate lines. This segmentation allows each bit to have optimized dimensions for programming efficiency while the combined structure achieves high storage density. Each segmented bit can be independently controlled and programmed, maintaining high programming efficiency for each bit while doubling the storage capacity per physical location.

The patent transitions from storing one bit per memory unit location to storing two bits per location by adding the dimension of dual-bit storage. This is achieved through the split-gate structure where two control-gate lines (CG1 and CG2) control two separate memory bits at each memory unit location, effectively doubling storage density without proportionally increasing the area occupied by each individual memory bit.