Peripheral Voltage Control Circuit for Semiconductor Memory Leakage Reduction
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Solution Overview
Problem
Semiconductor memory devices face issues with leakage currents due to gate residue, leading to increased standby current and reduced precharge performance, and the existing voltage control circuits occupy space in the core region, limiting transistor size and increasing device area.
Innovation Solution
A voltage control circuit and method that selectively provides bit line precharge voltages to minimize leakage current by arranging the voltage control circuit in the peripheral region, allowing for different voltage modes and eliminating the need for a metal line to apply bleed voltage, thereby enhancing area efficiency and precharge performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a voltage control circuit is arranged in the core region to control bleed voltage, then leakage current can be reduced, but the size of other transistors controlling the core is reduced, decreasing core performance
Solution Approach 1:
The voltage control circuit is extracted from the core region and relocated to the peripheral region. This separation allows the core region to be dedicated solely to core transistors and operations, eliminating the space constraint that reduced transistor size. The peripheral region houses the voltage control circuit that generates and controls bleed voltage, thereby reducing leakage current without compromising core performance.
Solution Approach 2:
The patent reorganizes the spatial layout by moving the voltage control circuit from the horizontal plane of the core region to the peripheral region, effectively utilizing unused space in another dimension. This dimensional reorganization allows both the voltage control circuit and core transistors to operate at full size without spatial interference.
2Object-generated harmful factors
If the voltage control circuit is arranged in the core region, then bleed voltage can be controlled, but the total area of the semiconductor memory device is increased due to extended metal line length
Solution Approach 1:
The voltage control circuit is extracted from the core region and placed in the peripheral region, which eliminates the need for long metal lines to traverse the core region. The peripheral region is naturally positioned to provide shorter connection paths, thereby reducing the overall metal line length and minimizing the additional area required.
3Object-generated harmful factors
If a fixed bleed voltage is applied irrespective of active and standby states, then leakage current can be reduced in standby state, but the time to precharge bit lines in active state is increased, lowering precharge performance
Solution Approach 1:
The voltage control circuit implements dynamic voltage control by providing different voltage levels depending on the operational state. In the standby state, it applies a first voltage level to minimize leakage current. In the active state, it switches to a second voltage level that enables faster precharging of bit lines. This dynamic adaptation resolves the contradiction between leakage reduction and precharge performance.
Solution Approach 2:
The patent changes the voltage parameter based on operational requirements. By switching between a first voltage level (for standby state leakage reduction) and a second voltage level (for active state precharging), the system optimizes both leakage current control and precharge performance without compromise.
Data Source
AI summary
A semiconductor memory device includes a voltage control circuit providing different voltages as a precharge voltage in accordance with an active state and a standby stage. The semiconductor memory device is arranged in a peripheral region, whereby the different voltages can be provided as a precharge voltage in accordance with the active state and the standby state and thus leakage current is reduced and area efficiency is enhanced.