Semiconductor Memory Device Edge Sense Amplifier Reference Data
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Solution Overview
Problem
FBC memory devices face a decrease in memory capacity due to the need for a double-ended sense amplifier arrangement in crosspoint configurations, similar to DRAM, which limits their operational efficiency in one-cell/bit mode.
Innovation Solution
The semiconductor memory device employs a configuration with multiple memory cell arrays, alternating bit lines, and edge arrays generating reference data, allowing edge sense amplifiers to detect data from memory cell arrays based on reference data from edge arrays, optimizing data detection and reducing capacity loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a double-ended sense amplifier arrangement is used in crosspoint configuration, then data detection capability is maintained, but memory capacity decreases due to limited connection to furthest memory-cell array
Solution Approach 1:
The memory device is divided into multiple memory cell arrays (first, second, and third arrays) arranged in sequence, with sense amplifiers positioned between them. This segmentation allows each sense amplifier to serve multiple arrays, effectively increasing the usable memory capacity while maintaining detection capability through the alternating bit line configuration.
Solution Approach 2:
The patent introduces a spatial arrangement dimension by positioning memory cell arrays in a sequence rather than a traditional two-dimensional grid. The first, second, and third memory cell arrays are arranged in a linear sequence with sense amplifiers placed between them, enabling bit lines to alternate between arrays and create additional connection pathways that increase capacity without sacrificing detection precision.
2Quantity of substance
If alternating bit lines are connected to multiple memory cell arrays, then memory capacity is increased, but bit line capacitance becomes unbalanced causing detection errors
Solution Approach 1:
Edge arrays are introduced as intermediary structures positioned at the boundaries of the memory cell arrays. These edge arrays generate reference data that acts as a mediator between the bit lines and the sense amplifiers, compensating for capacitance imbalances caused by the alternating bit line configuration across multiple arrays.
Solution Approach 2:
The patent modifies the electrical parameters of the bit lines by introducing edge arrays that generate reference data signals. This changes the electrical environment of the bit lines, providing reference signals that normalize the capacitance effects and enable accurate detection despite the unbalanced configuration caused by connecting bit lines to multiple memory cell arrays.
3Measurement precision
If edge arrays with reference data generation are added, then data detection accuracy is improved, but device complexity increases
Solution Approach 1:
The edge arrays serve multiple functions: they generate reference data for the bit lines, compensate for capacitance imbalances, and enable accurate detection across all memory cell arrays. By making the edge arrays multi-functional, the patent improves detection accuracy without proportionally increasing complexity, as these structures perform several critical roles simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances data detection accuracy and efficiency, preventing errors from capacitance coupling and maintaining high operational speed, even with unbalanced bit line capacitances, thereby improving memory capacity and access time.
Implementation Method 1
The FBC memory device stores data '1' or data '0' based on the number of majority carriers accumulated in this body
Implementation Method 2
each first sense amplifier detecting data from one of the two memory cell arrays on the basis of reference data from the other of the two memory cell arrays
Data Source
AI summary
A memory includes: first sense amplifiers arranged in a first interval of an arrangement of memory cell arrays, each being connected to first bit lines corresponding to two memory cell arrays provided at both sides of the first sense amplifier; second sense amplifiers arranged in a second interval of the arrangement of the memory cell arrays, each being connected to second bit lines corresponding to two memory cell arrays at both sides of the second sense amplifier; edge arrays provided beside both ends of an arrangement of the memory cell arrays, the edge arrays generating only the reference data; and edge sense amplifiers provided between the arrangement of the memory cell arrays and the edge arrays, wherein the edge sense amplifier detects data from the memory cell array at one end of the memory cell arrays based on the reference data from one of the edge arrays.