Spurious Charge Cleanup in OTP Memory via Shunt Device
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Solution Overview
Problem
Conventional one time programmable (OTP) memory cells in RFID applications face issues with high circuit impedances, small capacitance values, and spurious charge induction, leading to incorrect data storage results and high power consumption in low-power applications like passive UHF RFID tags.
Innovation Solution
A high density, low voltage, and low-power OTP memory design using a one transistor core cell with a CLEAN pulse directed to a single shunt device at the output of the column decoder for spurious charge cleanup, allowing simultaneous initialization of bit lines, data lines, and sensing lines to zero, reducing layout size and power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional OTP memory cells with high circuit impedances and small capacitance values are used, then memory density is improved, but spurious charges are induced causing incorrect data storage results
Solution Approach 1:
The patent applies a CLEAN pulse to the floating node before the actual write operation to remove any pre-existing spurious charges. This preliminary cleaning action ensures that the floating node starts in a known clean state, preventing incorrect data storage results while maintaining high memory density with small capacitance values
Solution Approach 2:
The patent converts the harmful effect of spurious charge induction into a beneficial cleaning mechanism by deliberately applying a controlled CLEAN pulse that removes unwanted charges. The same floating node structure that is susceptible to spurious charges is used, but the harmful charges are converted into a cleaning opportunity through the applied pulse sequence
2Reliability
If clean up pulses are applied broadly to nullify spurious charges, then data storage accuracy is improved, but power consumption increases
Solution Approach 1:
The patent applies the CLEAN pulse locally and selectively to only the specific floating nodes that require cleaning, rather than broadly to all nodes. The column decoder enables targeted application of the clean-up pulse to minimal necessary locations, reducing overall power consumption while maintaining data storage accuracy
Solution Approach 2:
The patent uses a controlled CLEAN pulse with sufficient amplitude and duration to remove spurious charges, but applies it only partially to the minimal set of nodes that need cleaning rather than to all nodes. This partial action approach reduces power consumption compared to a comprehensive broad application
3Reliability
If special circuits and additional devices are added to clean up spurious charges, then data storage accuracy is improved, but layout size and manufacturing cost increase
Solution Approach 1:
The patent makes the existing column decoder and output transistors multi-functional by using them to generate and apply CLEAN pulses in addition to their normal decode and drive functions. This eliminates the need for separate dedicated clean-up circuits, maintaining data storage accuracy without increasing layout size
Solution Approach 2:
The patent merges the spurious charge cleaning function with the existing column decoder and output transistor structure. The CLEAN pulse generation and application is combined with the normal memory operation circuitry, eliminating the need for separate special circuits and reducing overall layout size
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively cleans spurious charges, reduces operational power, and minimizes layout size, making it suitable for UHF RFID applications with significant power savings and compact design.
Implementation Method 1
A CLEAN pulse is directed to a single shunt device at the output of the column decoder so spurious charges that may have been stored in the floating nodes can be cleaned up
Data Source
AI summary
A high density, low voltage, and low-power one time programmable (OTP) memory is based on core cells with a one transistor design. A CLEAN pulse is directed to a single shunt device at the output of the column decoder so spurious charges that may have been stored in the floating nodes can be cleaned up. Such arrangement also allows for the simultaneous initialization of bit lines, data lines, and sensing lines to zero. Core area layout size is substantially reduced, and operational power requirements are exceeding low making these particularly suitable in HF and UHF RFID applications.