Variable Reference Voltage Circuit for SONOS Memory Endurance
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Solution Overview
Problem
SONOS non-volatile memory cells face endurance and retention degradation due to operational stresses from programming and erasing voltages, as well as elevated temperatures, leading to reduced lifespan and inability to retain data effectively.
Innovation Solution
A variable reference voltage circuit that decouples write voltages for programming, erasing, and reading operations, allowing for independent selection of optimal voltages for each operation to enhance endurance and retention, using a multi-level voltage source and selector circuit to apply specific voltages based on the memory operation being performed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single reference voltage is used for all memory operations, then the circuit complexity is reduced, but the endurance and retention of the memory cell deteriorates due to suboptimal voltage selection for specific operations
Solution Approach 1:
The patent divides the single reference voltage into multiple distinct reference voltages (first reference voltage for programming, second reference voltage for erasing, third reference voltage for reading). This segmentation allows each memory operation to receive its own optimized voltage level, thereby improving endurance and retention without using a single compromised voltage for all operations.
Solution Approach 2:
The patent implements a dynamic voltage selection mechanism where the reference voltage is changed based on the specific memory operation being performed. The controller selectively switches between different reference voltages (Vref1 for program, Vref2 for erase, Vref3 for read) to match the operational requirements of each memory cell state manipulation.
2Reliability
If higher voltages are applied to ensure data retention, then the retention capability improves, but the operational stresses on the memory cell increase leading to reduced lifespan
Solution Approach 1:
The patent applies different voltage levels tailored to specific local operations: a first reference voltage optimized for programming operations, a second reference voltage optimized for erasing operations, and a third reference voltage optimized for reading operations. Each voltage level is locally optimized for its specific function, preventing excessive operational stresses that would occur with uniform high-voltage application.
Solution Approach 2:
The patent changes the voltage parameter dynamically based on the memory operation type. By adjusting the reference voltage parameter from Vref1 during programming, to Vref2 during erasing, and Vref3 during reading, the system optimizes the balance between achieving necessary data retention and minimizing operational stresses that would degrade memory cell lifespan.
Data Source
AI summary
A variable reference voltage circuit for performing memory operation on non-volatile memory includes a multi-level voltage source and a selector circuit. The multi-level voltage source generates multiple voltages. The selector circuit includes a selector input and a selector output. The selector input is coupled to the multi-level voltage source to selectively couple any of the multiple voltages to the selector output. The selector output of the selector circuit is coupled to a non-volatile memory array to provide the NV memory array with a selectable program voltage for programming the NV memory array and a selectable erase voltage for erasing the NV memory array.