Memory Data Reception With Adaptive Clocking for Lower Power
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Solution Overview
Problem
Computing devices face challenges in reducing power consumption, particularly in memory systems, as existing clocking schemes continue to consume power even during low-speed data communications.
Innovation Solution
Implementing an internal clock generated by the host to receive data, allowing the host to disable the data clock during low-speed operations, thereby reducing power consumption by eliminating the need for a synchronized data clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a synchronized data clock is used to receive data from memory, then data reception reliability is improved, but power consumption increases
Solution Approach 1:
The system dynamically switches between two clocking modes: using a synchronized data clock for high-speed data reception and using an internally generated clock for low-speed data reception. This dynamic adaptation allows the system to optimize power consumption based on actual data transfer requirements while maintaining reliable data reception when needed.
Solution Approach 2:
The invention changes the clocking parameter from always using an externally synchronized clock to conditionally using either an external clock or an internally generated clock based on data transfer speed requirements. This parameter change enables power savings during low-speed operations while preserving the ability to use synchronized clocking when high reliability is required.
2Use of energy by moving object
If an internally generated clock is used to receive data, then power consumption is reduced, but clock synchronization capability deteriorates
Solution Approach 1:
The system dynamically selects the appropriate clock source based on operational requirements. During low-speed data transfers, it uses the internally generated clock to save power. During high-speed or critical data transfers, it switches to using the externally synchronized clock to ensure proper timing and synchronization. This dynamic selection resolves the contradiction between power savings and synchronization capability.
Solution Approach 2:
The internally generated clock acts as an intermediary solution that provides adequate timing for low-speed operations without requiring the power-consuming external clock circuitry. It serves as a suitable substitute during periods when full synchronization capability is not required, enabling power savings while maintaining system functionality.
3Use of energy by moving object
If data clock is disabled during low-speed operations, then power consumption is reduced, but data reception flexibility deteriorates
Solution Approach 1:
The system dynamically adjusts its clocking strategy based on data transfer speed requirements. During low-speed operations, it disables the external data clock to save power while using the internal clock for timing. During high-speed or variable-speed operations, it enables the external clock to provide the necessary timing flexibility. This dynamic adaptation maintains data reception flexibility while optimizing power consumption.
Solution Approach 2:
The internally generated clock is designed to provide universal timing capability that can handle both low-speed and, when needed in combination with external clock signals, high-speed data reception. This multi-functional clocking approach ensures that the system maintains adaptability across different operating conditions while minimizing power consumption during low-speed operations.
Data Source
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AI summary
Methods and apparatuses for improve clocking scheme to reduce power consumption are presented. The apparatus includes a host configured to communicate with a memory via a link. The host is further configured to receive a first clock from the memory; to receive, based on the first clock, data from the memory, in a first mode of a read operation; to generate a second clock, the second clock being generated independent of the first clock; and to receive, based on the second clock, data from the memory, in a second mode of the read operation.