Generating/Distributing Signals TRIZ Cases
- Wireline Transceiver With Selectable Internal and External Clocks
See how a wireline transceiver switches between external and calibrated onboard clocks to balance accuracy, size, cost, and power.
- Digital In-Memory Compute Chiplets for Low-Latency LLM Inference
Digital in-memory compute chiplets combine local processing, BFP numerics, and die-to-die links to address LLM throughput and bandwidth limits.
- Camera Sensor Clock Gating to Reduce Idle Power Leakage
Selective clock gating activates needed camera sensors while reducing leakage from inactive hardware in XR, AR, and MR devices.
- Redundant Clock Managers for Secure TSN Time Synchronization
A physics-based detector identifies compromised clock-manager behavior and triggers redundant failover to preserve accurate TSN time synchronization.
- Chassis Component Time Synchronization via Shared Profiles
Mismatched chassis time settings can disrupt updates and communication; a shared profile aligns settings across components.
- Workload-Aware Processor Configuration API for Resource Scheduling
Static job scheduling can waste computing resources; this API matches processor frequency, voltage, and power states to workload needs.
- Local Clock-Buffer Detuning on Continuous Clock Grids
Reducing buffer drive strength in unused clock-mesh regions saves power while preserving synchrony across active circuitry.
- Gateway DDR Memory Clock Tuning to Reduce 2.4 GHz Wi-Fi Noise
Reducing 32-bit DDR memory from 1600 MHz to 1067 MHz shifts harmonics away from 2.4 GHz Wi-Fi and cuts noise by 15–20 dB.
- Mobile Media Recording With Pinned Albums And Auto-Organized Files
Automatic album pinning stores new photos, videos, and audio in the active album, while timed resets and cleanup limit redundant folders.
- Clock Tree Variation Measurement and Compensation for IC Latency
Counter and synchronizer circuits measure clock differences, enabling dynamic compensation for voltage-temperature variation and lower IC latency.
- Instruction-Decoded Clock Waveform Synthesis for Fine-Grain Power Management
Instruction decoding enables per-cycle clock-period and duty-cycle adjustment, improving power responsiveness, latency, and throughput in high-speed processors.