Local Clock-Buffer Detuning on Continuous Clock Grids
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Solution Overview
Problem
Clock meshes in integrated circuits waste power by driving clock signals to unused circuitry, and previous techniques like clock gating are ineffective due to timing issues with large meshes.
Innovation Solution
Reduce the strength of clock buffers providing signals to unused circuitry within the clock mesh, allowing the buffers to continue operating at a lower power level without disrupting active circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock gating is used to stop the clock signal in certain regions of the IC, then power consumption is reduced, but timing skew is introduced that disrupts clock synchronicity in other circuitry
Solution Approach 1:
The patent changes the strength parameter of clock buffers dynamically based on circuit activity. Clock buffers serving unused circuitry reduce their drive strength to minimize power consumption, while buffers serving active circuitry maintain full strength to ensure proper timing. This parameter adjustment allows partial operation of clock buffers rather than complete on/off switching, thereby avoiding timing skew issues.
Solution Approach 2:
The patent applies different operational characteristics to different regions of the clock mesh based on local circuit activity. Each clock buffer operates with a strength appropriate to its local region's needs - reduced strength for unused regions, full strength for active regions. This local differentiation allows power savings in inactive areas without compromising timing in active areas.
2Use of energy by moving object
If the strength of clock buffers is reduced for unused circuitry, then power consumption is saved, but clock signal strength may become insufficient
Solution Approach 1:
The patent dynamically adjusts the drive strength parameter of clock buffers based on the activity state of served circuitry. For unused circuitry, buffer strength is reduced to save power while maintaining sufficient clock signal levels. For active circuitry, buffer strength remains at full levels to ensure adequate signal drive capability. This adaptive parameter adjustment resolves the contradiction between power savings and signal strength.
Data Source
AI summary
Embodiments herein describe changing the strength of clock buffers used to drive different portions of a clock mesh. In one embodiment, the clock mesh may provide a clock signal to multiple different circuit elements in an integrated circuit. If one circuit element is not being used (e.g., a CPU does not need to use one of its cores), the clock buffer (or buffers) for the portion of the clock mesh that provides a clock signal to the circuit element can have its strength reduced, thereby saving power.