Adaptive Memory Testing for Server Boot Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing size of memory in computers and the need for stricter memory testing to ensure system reliability lead to a burden on server boot performance, as existing BIOS memory testing methods often compromise between reliability and performance by using a single test loop or arbitrary test patterns.
Innovation Solution
A method and system for memory testing in a server computer system that adjusts the number of test loops and test patterns based on past memory test results, allowing for optimized hardware memory testing during the boot process, potentially skipping or reducing the number of test loops and patterns if the system is stable, thereby improving boot efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stricter and broader memory testing is performed to ensure system reliability, then memory testing coverage and reliability are improved, but server boot efficiency deteriorates
Solution Approach 1:
The patent applies dynamics by making the memory test configuration adjustable and adaptive rather than fixed. The system dynamically determines the number of test loops and selects test patterns based on memory size, allowing the testing process to adapt to different memory configurations and optimize the balance between reliability and boot efficiency.
Solution Approach 2:
The patent changes parameters (number of test loops, test pattern selection) based on memory size thresholds. By establishing corresponding relationships between memory size ranges and test configurations, the system adjusts testing intensity appropriately, ensuring sufficient reliability for larger memories while maintaining boot efficiency for smaller configurations.
2Quantity of substance
If memory size increases to provide larger data processing capability, then data processing capability is improved, but memory testing burden increases
Solution Approach 1:
The patent segments the memory testing process by dividing it into multiple test loops with different patterns. Each test loop targets specific aspects of memory functionality, allowing comprehensive testing of large memory capacities while organizing the complexity into manageable, structured phases.
Solution Approach 2:
The system dynamically adjusts the number of test loops and pattern selection based on detected memory size. This dynamic adaptation ensures that testing burden scales appropriately with memory capacity, providing thorough testing for larger configurations without unnecessarily complicating the process for smaller memories.
Data Source
AI summary
In a method of memory testing in a data processing system, in response to receiving a request for a hardware memory test during boot process of the data processing system, a controller accesses a stored past memory test result. The past memory test result includes at least a first number of test loops used in a past memory test, an identification of a first test pattern, and an error that occurred in the past memory test. The controller adjusts a second number of test loops and a second test pattern to be used in the hardware memory test according to the past memory test result. The controller then performs the hardware memory test according to the adjusted second number of test loops and the second test pattern.