Static Storage TRIZ Cases
- BCAM Segmentation for Fast ECC Data Search
Segmenting a binary content addressable memory into sub-BCAMs enables fast searching of ECC protected data without full error correction overhead.
- Per-row Error Scrub Registers for Memory Data Fidelity
Per-row error scrub registers collect granular error data within memory arrays to support targeted correction operations.
- Semiconductor Test Delay Compensator for Turnaround Variations
A test apparatus delay compensator generates delayed read data by calculating the difference between external and internal turnaround delay values.
- Internal Voltage Generating Circuit with Segmented Resistors
Segmented pull-up and pull-down resistors activate low resistance for fast voltage setting while maintaining high resistance to reduce current consumption.
- 3D Stacked Memory Via Testing With Dynamic Chip IDs
Dynamic chip IDs isolate faulty through-chip vias in stacked semiconductor memory, resolving complex fault detection challenges.
- On-Chip SerDes Eye Monitor for Signal Integrity Characterization
Looping back the transmit signal to an integrated receiver-side monitor eliminates off-chip signal loss and interference during SerDes PHY testing.
- Radiation-Hardened Memory Circuit with EDAC and Segmented Scrubbing
Segmented error detection and correction circuits reduce single-bit failures in radiation-exposed CMOS systems without increasing processing time.
- Parallel Memory Test Circuit with Module Selection and Comparator
A semiconductor device uses a module selection circuit to collectively select multiple memory modules for parallel testing via a comparator.
- Dynamic Memory Signal Phase Tracking for DDR Data Strobe
A memory controller adjusts the data strobe signal phase to maintain accurate data access.
- Grown Bad Block Management in Memory Sub-systems
A memory sub-system maintains a replacement block pool to migrate data from grown bad blocks.
- Memory Defect Map for System Reliability Optimization
A memory defect map identifies defective locations to optimize system performance and integrity.
- Variable ECC Codeword Sizes for SSD Flash Memory Optimization
A solid-state drive controller divides host data units into variable-sized payloads encoded as distinct codewords to maximize storage density.
- Semiconductor Device Internal-Potential Force Circuit for Leak Current Prevention
Internal-potential force circuit disconnects nodes via switch elements to prevent leak currents during wafer testing.
- Voltage Detection Circuit for Multi-Supply Protection
A voltage detection circuit monitors multiple power rails to trigger protection operations when levels fall outside operating ranges.
- Multi-Interface Memory Card Selective Reset Control
A memory card resets individual function blocks via interface-specific signals to maintain active communication channels.
- Memory Clock Signal Tolerance Test System
A signal providing module generates symmetrical and asymmetrical clock signals for memory testing.
- Memory Device Multi-Bit Error Self-Repair via Segmented Reading Cycles
Segmented reading cycles detect multiple erroneous bits in memory cells, triggering self-repair by replacing defective units with repairing cells.
- Redundancy Circuit Repair Location Prediction for IC Yield
Determines final repair locations by identifying potential fail lines and predicted sites, reducing new fail bit occurrence and improving chip production yield.